CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet
CYNSE70256-66BHC
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CYNSE70256-66BHC Summary of contents
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... CYNSE70256 Network Search Engine Cypress Semiconductor Corporation Document #: 38-02035 Rev. *E • 3901 North First Street • CYNSE70256 , San Jose CA 95134 • 408-943-2600 Revised December 12, 2003 ...
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... SRAM PIO Access ........................................................................................................................ 86 12.2 SRAM Read with a Table Four Devices .......................................................................... 87 12.3 SRAM Read with a Table Fifteen Devices ....................................................................... 89 12.4 SRAM Write with a Table Four Devices .......................................................................... 90 12.5 SRAM Write with Table(s) Consisting Fifteen Devices .................................................... 92 Document #: 38-02035 Rev. *E CONTENTS CYNSE70256 Page 2 of 109 ...
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... Power-up Sequence ..................................................................................................................... 94 13.2 Power Consumption ..................................................................................................................... 95 14.0 APPLICATION ............................................................................................................................. 95 15.0 JTAG (1149.1) TESTING ............................................................................................................. 96 16.0 ELECTRICAL SPECIFICATIONS ................................................................................................ 97 17.0 AC TIMING WAVEFORMS .......................................................................................................... 98 18.0 PINOUT DESCRIPTIONS AND PACKAGE DIAGRAMS ......................................................... 102 19.0 ORDERING INFORMATION ...................................................................................................... 107 20.0 PACKAGE DIAGRAM ................................................................................................................ 107 Document #: 38-02035 Rev. *E CONTENTS (continued) CYNSE70256 Page 3 of 109 ...
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... Figure 7-1. Comparand Register Selection during Search and Learn Instructions ............................... 14 Figure 7-2. Addressing the GMR Array ................................................................................................. 14 Figure 8-1. CYNSE70256 Database Width Configuration for Each of the Two Banks .......................... 17 Figure 8-2. Multiwidth Database Configurations Example ..................................................................... 18 Figure 9-1. Addressing the CYNSE70256 Data and Mask Arrays ........................................................ 19 Figure 10-1 ...
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... Figure 12-10. Table of Fifteen Devices (Four Blocks) ........................................................................... 93 Figure 12-11. SRAM Write Through Device Number 0 in Bank of Fifteen Devices (Device 0 Timing)........................................................................................ 93 Figure 12-12. SRAM Write Through Device Number 0 in Bank of Fifteen CYNSE70256 Devices (Device Number 14 Timing)................................................. 94 Document #: 38-02035 Rev. *E LIST OF FIGURES (continued) ...
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... Figure 14-1. Sample Switch/Router Using the CYNSE70256 Device ................................................... 96 Figure 17-1. Input Wave Form for CYNSE70256 .................................................................................. 99 Figure 17-2. Output Load for CYNSE70256 .......................................................................................... 99 Figure 17-3. 2.5 I/O Output Load Equivalent for CYNSE70256 ............................................................ 99 Figure 17-4. AC Timing Wave Forms with CLK2X .............................................................................. 100 Figure 17-5. AC Timing Wave Forms with CLK1X .............................................................................. 101 Figure 18-1 ...
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... Table 16-2. Operating Conditions for CYNSE70256 ............................................................................ 97 Table 17-1. AC Timing Parameters with CLK2X .................................................................................. 98 Table 17-2. AC Timing Parameters with CLK1X .................................................................................. 98 Table 17-3. AC Table for Test Condition of CYNSE70256 ................................................................... 99 Table 18-1. Pinout Descriptions for Pinout Diagram ........................................................................... 102 Table 19-1. Ordering Information ........................................................................................................ 107 Document #: 38-02035 Rev. *E ...
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... Associative Processing Technology™ (APT) and is designed high-performance, pipelined, synchronous, 256K-entry NSE. The CYNSE70256 database entry size can be 72 bits, 144 bits, or 288 bits. In the 72-bit entry mode, the size of the database is 128K entries. In the 144-bit mode, the size of the database is 64K entries, and in the 288-bit mode, the size of the database is 32K entries ...
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... Data Array Configurable as 128K × 72 64K × 144 32K × 288 Mask Array LHI[6:0] Arbitration BHI[2:0] Logic FULL FULO[1:0] Figure 2-1. CYNSE70256 Block Diagram CYNSE70256 Bank 1 Bank 0 TAP Controller SADR[23:0] OE_L Pipeline and WE_L SRAM Control CE_L ...
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... Depending on the CLK_MODE pin, either the CLK2X or the CLK1X must Master Clock be supplied. CYNSE70256 samples control and data signals on both edges of CLK1X (if CLK1X is supplied). CYNSE70256 samples all data and control pins on the positive edge of CLK2X (if the CLK2X and PHS_L signals are supplied). All signals are driven out of the device on the rising edge of CLK1X (if CLK1X is supplied), and are driven on the rising edge of CLK2X when PHS_L is LOW (if CLK2X is supplied) ...
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... When this signal is LOW, the addresses are valid on the SRAM Address Latch Enable address bus database of multiple CYNSE70256s, the ALE_L of all cascaded devices must be connected. This signal is then driven by only one of the devices. . These pins depth-cascade the device to form a larger table. One signal of Local Hit In this bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block ...
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... I TDO T TMS I TRST_L I 5.0 Clocks If the CLK_MODE pin is LOW, CYNSE70256 receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X [3, 4] and generate an internal clock (CLK tions. CLK2X PHS_L [4] CLK Figure 5-1. CYNSE70256 Clocks (CLK2X and PHS_L) If the CLK_MODE pin is HIGH, CYNSE70256 receives CLK1X only. CYNSE70256 uses an internal phase-lock loop (PLL) to double the frequency of CLK1X and then divides that clock by two to generate a CLK for internal operations, as shown in Figure 5-2 ...
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... Registers All registers in the CYNSE70256 device are 72 bits wide. The CYNSE70256 contains two banks of sixteen pairs of comparand storage registers, sixteen pairs of GMRs, eight search successful index registers, and one each of command, information, burst Read, burst Write, and next-free address registers. Table 7-1 provides an overview of all the CYNSE70256 registers. The registers are in ascending address order ...
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... In 72-bit Search and Write operations, the host ASIC must program both the even and odd mask registers with the same values for each of the banks. Document #: 38-02035 Rev. *E Address 72 72 index 143 Index 143 Search and Write Command Global Mask Selection Figure 7-2. Addressing the GMR Array CYNSE70256 0 [ Page 14 of 109 ...
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... Last Device on the SRAM Bus in the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L signals. In cycles where no CYNSE70256 device in a depth-cascaded table drives these signals, this drives the signals as follows: SADR = 23’hFFFFFF, CE_L = 1, WE_L = 1, and ALE_L = 1. OE_L is always driven by the device for which this bit is set. ...
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... The device is divided internally into two banks each consisting of sixteen . Initial Value Revision Number Numbers start at one and increment by one for each revision of the device. This is the CYNSE70256 implementation number. . Reserved This is the device identification number. Manufacturer ID fication number and continuation bits in the TAP controller. ...
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... Every Write and/or Learn command loads the address of the first 72-bit location that contains the entry’s bit[0]. This is stored in the NFA register(see Table 7-7). If all the bits[ device for both the banks within the device are set to 1, the CYNSE70256 asserts FULO[1: ...
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... The global winning device drives the SRAM bus, the SSV, and the SSF signals. In case of a Search failure, the device(s) with a bank with the LDEV and LRAM bits set drives the SRAM bus, SSF, and SSV signals. The CYNSE70256 device can be configured to contain tables of different widths, even within the same chip. Figure 8-2 shows a sample configuration of different widths. ...
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... Figure 9-1. Addressing the CYNSE70256 Data and Mask Arrays 10.0 Commands A master device such as an ASIC controller issues commands to the CYNSE70256 device using the CMDV signal and the command bus. The following subsections describe the operation of these commands. 10.1 Command Codes The CYNSE70256 device implements four basic commands, as shown in Table 10-1 ...
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... Reads a block of locations from the data or mask array as a burst. RBURADR specifies the starting address and the length of the data transfer from the data or mask array; it also auto-increments the address for each access. All other access information is applied on [10] the DQ bus. CYNSE70256 ...
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... Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[ using CMDV = 1, and the DQ bus supplies the address, as shown in Table 10-4 and Table 10-5. The host ASIC selects the CYNSE70256 device for which ID[4:1] matches the DQ[25:22] lines. The DQ[21] specifies the bank of the device. If DQ[25:21] = 11111, the host ASIC selects the CYNSE70256 with the LDEV bit set ...
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... Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[ using CMDV = 1, and the address supplied on the DQ bus as shown in Table 10-6. The host ASIC selects the bank (Based on Bank Bit) of the CYNSE70256 device where ID[4:1] matches the DQ[25:22] lines. DQ[21] specfies the bank of the device that is written. If DQ[25:21] = 11111 the host ASIC selects the bank of the CYNSE70256 device with the LDEV bit set. • ...
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... Mask Array Reserved If DQ[29 this field carries the address Bank 10: External Reserved If DQ[29 this field carries the address SRAM DQ[21] DQ[20:19] Bank 11: Register CYNSE70256 cycle 3 cycle [15:0] the data array location. If DQ[29 the SSR specified on DQ[28:26] is used to generate the address of data array location: {SSR[15:2], SSR[1] | [14] DQ[1], SSR[0] | DQ[0]}. ...
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... The CYNSE70256 device writes the data on the DQ[71:0] bus only to the subfield that has the corresponding mask bit set the GMR specified by the index supplied in cycle 1 {CMD[10],CMD[5:3]}. The CYNSE70256 device drives the EOT signal LOW from cycle 3 to cycle n; the CYNSE70256 device drives the EOT signal HIGH in cycle specified in the BLEN field of the WBURREG). ...
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... Mixed-size search on tables configured with different widths using an CYNSE70256 with CFG_L LOW • Mixed-size searches on tables configured with different widths using an CYNSE70256 with CFG_L HIGH. 10.6.1 72-bit Search on Tables Configured as ×72 using up to Four CYNSE70256 Devices The hardware diagram of the Search subsystem of four devices is shown in Figure 10-5 ...
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... Note: |LHO[1:0] is logical “or” of LHO[0] and LHO[1]. Figure 10-6. Timing Diagram for 72-bit Search Device Number 0 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (This (This device is device is ...
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... Note: |LHO[1:0] is logical “or” of LHO[0] and LHO[1]. Figure 10-7. Timing Diagram for 72-bit Search Device Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss (Local on this winner device.) but not global winner.) ...
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... Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70256 cycle cycle cycle Search3 Search1 (Local (Miss on winner but this device.) not global winner ...
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... The hardware diagram of the Search subsystem of fifteen devices is shown in Figure 10-10. Each of the four blocks in the diagram represents four CYNSE70256 devices (except the last, which has three devices). The diagram for a block of four devices is shown in Figure 10-11. The following are the parameters programmed into the fifteen devices. ...
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... BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70256s Block 1 (Devices 4–7) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70256s Block 2 (Devices 8–11) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70256s Block 3 (Devices 12–14) BHO[2] BHO[1] CYNSE70256 3 4 Miss Miss Hit Miss Hit Miss Miss Miss ...
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... Note: |LHO[1:0] is logical “or” of LHO[0] and LHO[1]. Figure 10-12. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02035 Rev LHI CYNSE70256 # CYNSE70256 #1 LHO[ CYNSE70256 #2 LHO[ CYNSE70256 #3 LHO[1] cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 ...
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... Figure 10-13. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search4 Search2 (Miss on (Miss on this device.) this device.) Page 32 of 109 ...
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... Figure 10-14. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (This device this device.) global winner.) Search4 Search2 (Miss on (Miss on this device.) this device.) Page 33 of 109 ...
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... Figure 10-15. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 34 of 109 ...
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... Figure 10-16. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search4 Search2 (Miss on (Miss on this device.) this device.) Page 35 of 109 ...
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... Figure 10-17. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Hit but not this device.) winner.) Search2 Search4 (Miss on (Global this device ...
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... Figure 10-18. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 37 of 109 ...
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... Figure 10-19. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search4 Search2 (Miss on (Miss on this device.) this device.) Page 38 of 109 ...
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... Note: |LHO[1:0] is logical “or” of LHO[0] and LHO[1]. Figure 10-20. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Global (Miss on winner.) this device.) Search2 Search4 (Hit but not (Miss on global winner ...
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... Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 (Except the Last Device [Device 14]) CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 40 of 109 ...
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... Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle Search3 Search2 Search4 Search1 (Hit on some device above.) CYNSE70256 cycle cycle cycle Search3 (Hit on some device above.) Search4 Search2 (Hit on some (Global miss; this device above.) device default driver.) Page 41 of 109 ...
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... Search on Tables Configured as ×144 using up to Four CYNSE70256 Devices The hardware diagram of the Search subsystem of four devices is shown in Figure 10-24. The following are parameters that are programmed into the four devices. • First three devices (devices 0–2, banks 0 and 1): CFG = 0101010101010101, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0. ...
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... CMD[10:0] BHI[2:0] Figure 10-24. Hardware Diagram for a Table with Four Devices Document #: 38-02035 Rev Hit Miss Miss Hit Miss Miss Miss Miss 0 1 CYNSE70256 # CYNSE70256 #1 LHO[ CYNSE70256 #2 LHO[ CYNSE70256 #3 LHO[1] CYNSE70256 3 Hit Hit Miss Hit SRAM LHI LHO[1] LHO[ LHI LHO[ ...
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... Note: |LHO[1:0] is logical “or” of LHO[0] and LHO[1]. Figure 10-25. Timing Diagram for 144-bit Search Device Number 0 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (This device (This device is the global is the global winner ...
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... Figure 10-26. Timing Diagram for 144-bit Search Device Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Local but this device.) not global winner.) Search2 Search4 (This device (Miss on global winner ...
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... SSR[0:7]). The DQ[71:0] is driven with 72-bit data ([71:0]) compared against all odd locations. Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search3 Search1 (Local but (Miss on not global this device.) winner.) Search2 Search4 ...
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... Location 0 address 524,286 CFG = 0101010101010101 (144-bit configuration) Figure 10-28. ×144 Table with Four Devices Max Table Size 256K × 144 bits 960K × 144 bits CYNSE70256 0 Odd B 0 (First matching entry) Latency in CLK Cycles 5 6 Number of CLK Cycles Page 47 of 109 ...
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... The hardware diagram of the Search subsystem of fifteen devices is shown in Figure 10-29. Each of the four blocks in the diagram represents a block of four CYNSE70256 devices (except the last, which has three devices). The diagram for a block of four devices is shown in Figure 10-30. The following are the parameters programmed into the fifteen devices. ...
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... BHI[2:0] SSF, SSV BHI[2:0] DQ[71:0] BHI[2:0] CMDV CMD[10:0] Figure 10-30. Hardware Diagram for a Table with Four Devices Document #: 38-02035 Rev. *E BHI[2] BHI[1] Block of 8 CYNSE70256s Block 0 (devices 0–3) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70256s Block 1 (devices 4–7) BHO[2] BHO[1] BHI[2] ...
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... Figure 10-31. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 50 of 109 ...
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... Figure 10-32. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 51 of 109 ...
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... Figure 10-33. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (This device this device.) global winner.) Search2 Search4 (Miss on (Miss on this device ...
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... Figure 10-34. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 53 of 109 ...
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... Figure 10-35. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search4 Search2 (Miss on (Miss on this device.) this device.) Page 54 of 109 ...
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... Figure 10-36. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Hit but not this device.) winner.) Search2 Search4 (Global (Miss on winner ...
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... Figure 10-37. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 56 of 109 ...
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... Figure 10-38. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 57 of 109 ...
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... Figure 10-39. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70256 cycle cycle cycle Search1 Search3 (Global (Miss on winner.) this device.) Search2 Search4 (Hit but not (Miss on global winner ...
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... Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 Except Device 14 (the Last Device) CYNSE70256 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 59 of 109 ...
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... A. Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle Search3 Search2 Search4 (Hit on some device above.) CYNSE70256 cycle cycle cycle Search1 Search3 (Hit on some device above.) Search4 Search2 (Global miss; this (Hit on some device is default driver.) device above.) ...
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... Search on ×288-configured Tables using up to Four CYNSE70256 Devices The hardware diagram of the Search subsystem of four devices is shown in Figure 10-43. The following are the parameters programmed into the four devices. • First seven devices (devices 0–6, Bank 0 and 1): CFG = 1010101010101010, TLSZ = 01, HLAT = 000, LRAM = 0, and LDEV = 0. ...
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... BHI[2:0] DQ[71:0] BHI[2:0] CMDV CMD[10:0] Figure 10-43. Hardware Diagram for a Table with Four Devices Document #: 38-02035 Rev Hit Miss Miss Miss 0 1 CYNSE70256 # CYNSE70256 # CYNSE70256 #2 LHO[1] BHI[2: CYNSE70256 #3 LHO[1] CYNSE70256 2 Miss Miss Hit Miss Miss Miss Miss Miss LHI LHO[1] LHO[ ...
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... Figure 10-44. Timing Diagram for 288-bit Search Device Number 0 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 (This device is the global winner.) CYNSE70256 cycle cycle cycle Search2 Search3 (Miss on (Miss on this device.) this device.) Page 63 of 109 ...
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... Figure 10-45. Timing Diagram for 288-bit Search Device Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 (Miss on this device.) CYNSE70256 cycle cycle cycle Search2 Search3 (This device (Miss on global winner.) this device.) Page 64 of 109 ...
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... DQ data in cycles C and D. Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 (Miss on this device.) [21] CYNSE70256 cycle cycle cycle Search3 Search2 (Miss on (Global miss.) this device.) [23] ...
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... The hardware diagram of the Search subsystem of fifteen devices is shown in Figure 10-48. Each of the four blocks in the diagram represents a block of four CYNSE70256 devices except the last, which has three devices.The diagram for a block of four devices is shown in Figure 10-49. The following are the parameters programmed into the fifteen devices. ...
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... Block of 8 CYNSE70256s block 1 (devices 4–7) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] Block of 8 CYNSE70256s block 2 (devices 8–11) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] Block of 7 CYNSE70256s block 3 (devices 12–14) BHO[2] BHO[1] BHO[0] CYNSE70256 3 Miss Hit Hit Miss SRAM GND Page 67 of 109 ...
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... BHI[2:0] SSF, SSV BHI[2:0] DQ[71:0] BHI[2:0] CMDV CMD[10:0] Figure 10-49. Hardware Diagram for a Block Four Devices Document #: 38-02035 Rev CYNSE70256 # CYNSE70256 # CYNSE70256 #2 LHO[1] BHI[2: CYNSE70256 #3 LHO[1] CYNSE70256 LHI LHO[1] LHO[ LHI LHO[1] LHO[ LHI LHO[ BHO[0] LHI BHO[1] BHO[2] LHO[0] SRAM ...
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... Figure 10-50. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70256 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 69 of 109 ...
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... Figure 10-51. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70256 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 70 of 109 ...
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... Figure 10-52. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70256 cycle cycle cycle Search1 Search2 Search3 (This device is (Miss on (Miss on global winner.) this device.) this device.) Page 71 of 109 ...
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... Figure 10-53. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70256 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 72 of 109 ...
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... Figure 10-54. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70256 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device; hit in block 0 or block 1.) Page 73 of 109 ...
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... Note: |LHO[1:0] is logical “or” of LHO[0] and LHO[1]. Figure 10-55. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70256 cycle cycle cycle Search1 Search2 Search3 (Miss on (Global (Hit but not this device ...
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... Figure 10-56. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70256 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 75 of 109 ...
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... Figure 10-57. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70256 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 76 of 109 ...
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... Note: |LHO[1:0] is logical “or” of LHO[0] and LHO[1]. Figure 10-58. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70256 cycle cycle cycle Search1 Search2 Search3 (Global (Hit but not (Miss on global winner.) winner.) this device.) ...
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... Figure 10-59. Timing Diagram for Devices Below the Winning Device in Block Number 3 Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search1 Search3 Except Device 14 (Last Device) CYNSE70256 cycle cycle cycle Search1 Search2 Search3 (Miss on (Miss on (Miss on this device.) this device.) this device.) Page 78 of 109 ...
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... The CMD[2] signal must be driven to logic 0. Note: 25. CMD[ signals that the Search is a ×288-bit Search. CMD[8:6] is ignored in this cycle. Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Search2 Search1 Search3 CYNSE70256 cycle cycle cycle Search2 (Hit on some device above ...
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... Document #: 38-02035 Rev. *E 287 287 CFG = 1010101010101010 (288-bit configuration) Figure 10-61. ×288 Table with Fifteen Devices Max Table Size 128K × 288 bits 480K × 288 bits Number of CLK Cycles CYNSE70256 [27 Must be same in each of the 15 devices D 0 (First matching entry) Latency in CLK Cycles ...
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... The DQ[71:70] will each of the two A and B cycles of the ×72-bit Search (Search1). DQ[71:70 each of the A and B cycles of the ×144-bit Search (Search2). DQ[71:70 each of the and D cycles of the ×288-bit Search (Search3). By having table designation bits, the CYNSE70256 device enables the creation of many tables in a bank of NSEs of different widths. ...
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... The global FULL signal indicates to the table controller (the host ASIC) that all entries within a block are occupied and that no more entries can be learned. The CYNSE70256 device updates the signal after each Write or Learn command to a data array. The Learn command generates a Write cycle to the external SRAM, also using the NFA register as part of the SRAM address (see Section 12.0, “ ...
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... Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle cycle cycle Learn1 Learn2 X X Comp2 Comp1 X X 1A1B cycle cycle cycle cycle cycle cycle cycle Learn1 X Learn2 Comp2 Comp1 Latency in CLK Cycles CYNSE70256 cycle cycle cycle cycle cycle cycle Page 83 of 109 ...
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... Depth Cascading up to Fifteen Devices (Four Blocks) Figure 11-2 shows the cascading four blocks. Each block except the last contains up to four CYNSE70256 devices, and the interconnection within each with the cascading four devices in a block was shown in the previous subsection. ...
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... Block of 8 CYNSE70256s Block 1 (devices 4–7) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70256s Block 2 (devices 8–11) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70256s Block 3 (devices 12–14) BHO[2] BHO[1] Figure 11-2. Depth Cascading four Blocks CYNSE70256 BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] BHI[0] ...
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... Section 7.0, “Registers,” on page 13 of this datasheet describes the NFA and SSR registers. ADR[15:0] contains the address supplied on the DQ bus during PIO access to the CYNSE70256. Command bits 8, 7, and 6 {CMD[8:6]} are passed from the command to the SRAM address bus. See Section 10.0, “Commands,” on page 19, for more information. ID[4:0] is the ID of the device driving the SRAM bus (see Section 18.0, “ ...
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... The following explains the SRAM Read operation completed through a table four devices using the following parameter: TLSZ = 01. Figure 12-1 diagrams a block of four devices. The following assumes that SRAM access is successfully achieved through CYNSE70256 device number 0. Figure 12-2 and Figure 12-3 show timing diagrams for device number 0 and device number 3, respectively. ...
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... TLSZ = 01, HLAT = 000, LRAM = 1, LDEV = 1 Figure 12-3. SRAM Read Timing for Device Number Block of Four Devices Document #: 38-02035 Rev. *E cycle cycle cycle cycle Read Address cycle cycle cycle cycle Read Address CYNSE70256 cycle cycle cycle Address driven by selected CYNSE70256 cycle cycle Page 88 of 109 ...
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... TLSZ = 10. The hardware diagram is shown in Figure 12-4. The following assumes that SRAM access is being accomplished through CYNSE70256 device number 0, and that device number 0 is the selected device. Figure 12-5 and Figure 12-6 show the timing diagrams for device number 0 and device number 14, respectively. ...
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... The following explains the SRAM Write operation accomplished through a table( four devices with the following parameters ( TLSZ = 01). The hardware diagram for this table is shown in Figure 12-7. The following assumes that SRAM access is achieved through CYNSE70256 device number 0. Figure 12-8 and Figure 12-9 show the timing diagram for device number 0 and device number 3, respectively. ...
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... DQ[20:19] set select the SRAM address. • Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70256 device. • Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70256 device. ...
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... Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70256 device. • Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70256 device. At the end of cycle 3, a new command can begin. The Write is a pipelined operation, but the Write cycle appears at the SRAM bus with the same latency as that of a Search instruction, as measured from the second cycle of the Write command ...
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... BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70256s Block 1 (devices 4–7) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70256s Block 2 (devices 8–11) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70256s Block 3 (devices 12–14) BHO[2] BHO[1] cycle cycle cycle cycle cycle cycle cycle ...
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... ACK 0 SSV 0 SSF TLSZ = 10, HLAT = XXX, LRAM = 1, LDEV = 1 Figure 12-12. SRAM Write Through Device Number 0 in Bank of Fifteen CYNSE70256 13.0 Power CYNSE70256 has two separate power supplies, one for the core (V 13.1 Power-up Sequence Proper power-up sequence is required to correctly initialize the Cypress Network Search Engines before functional access to the device can begin ...
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... Search Hit and All Search Miss) assume the I/Os switch 50% of the time. Document #: 38-02035 Rev. *E PLL lock time, 0.5ms Figure 13-1. Power-up Sequence (CLK2x) TRST_L RST_L PLL lock time, 0.5ms Figure 13-2. Power-up Sequence (CLK1x) CYNSE70256 64 CLK2x cycles 64 CLK2x cycles Page 95 of 109 ...
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... Application Figure 14-1 shows how an NSE subsystem can be formed using a host ASIC and a CYNSE70256 bank. It also shows how this NSE subsystem is integrated in a switch or router. The CYNSE70256 device can access synchronous and asynchronous SRAMs by allowing the host ASIC to set the same HLAT parameter in all NSEs within a bank of NSEs. ...
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... To disable JTAG functionality, connect the TCK, TMS, and TDI pins toVDDQ through a pull-up, and TRST_L to ground through a pull-down. 16.0 Electrical Specifications This section describes the electrical specifications, capacitance, operating conditions, DC characteristics, and AC timing param- eters for the CYNSE70256 device (see Table 16-1 and Table 16-2). Table 16-1. DC Electrical Characteristics for CYNSE70256 Parameter Description ...
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... IN 37 MHz OUT 38. Minimum allowable applies to undershoot only. 39. Maximum allowable applies to overshoot only (V 40. Maximum allowable applies to overshoot only (V 41. Typical. 80% Compare utilization. 42. Please refer to “CYNSE70256 Airflow and Heat Sink Requirements” application note. Document #: 38-02035 Rev. *E Description Description [39] (2.5V) [38] (2.5V) [40] (3 ...
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... AC Timing Waveforms Table 17-1 and Table 17-2 show the AC timing parameters for the CYNSE70256 device. Table 17-3 shows the AC test conditions for the CYNSE70256 device. Figure 17-1 shows the input wave form for the CYNSE70256 device. Figure 17-2 and Figure 17-3 show the output load and output load equivalent of the CYNSE70256 device ...
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... Output reference levels (V =2.5V) DDQ Output load AC Load Figure 17-3. 2.5 I/O Output Load Equivalent for CYNSE70256 Notes: 49. Output loading is specified with CL = 5pF as in Figure 17-3. Transition is measured at ± 200 mV from steady state voltage. 50. The load used for testing is shown in Figure 17-3. ...
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... Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV. Signal Group 5: DQ, ACK, EOT. Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle IHCH t IHCH t IHCH t ICHCH t CKHOV t CKHOV t CKHSHZ t CKHSV t CKHSLZ Figure 17-4. AC Timing Wave Forms with CLK2X CYNSE70256 cycle cycle cycle cycle cycle CKHDZ t CKHDV Page 101 of 109 ...
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... Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV. Signal Group 5: DQ, ACK, EOT. Document #: 38-02035 Rev. *E cycle cycle cycle cycle cycle IHCH t IHCH t ICHCH t CKHOV t CKHOV t CKHSHZ t CKHSV t CKHSLZ Figure 17-5. AC Timing Wave Forms with CLK1X CYNSE70256 cycle cycle cycle cycle cycle CKHDZ t CKHDV Page 102 of 109 ...
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... AB24 I/O AB25 I/O AB26 I/O AB3 2.5V/3.3V AB4 I/O AC1 I/O AC10 I/O AC11 I/O AC12 Ground AC13 2.5V/3.3V AC14 Ground AC15 2.5V/3.3V AC16 CYNSE70256 LHO0 LHI6 LHI2 LHI0 ID3 ID1 ID0 TRST_L V LHO1 LHI4 LHI3 LHI1 ID4 ID2 TDO ...
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... AE4 1.5V AE5 1.5V AE6 1.5V AE7 Input AE8 Input AE9 1.5V AF1 1.5V AF10 1.5V AF11 1.5V AF12 1.5V AF13 No Connect AF14 CYNSE70256 Signal Name Signal Type V Ground SS V Ground SS V Ground SS EOT Output-T V Ground SS V Ground SS V Ground SS V ...
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... C25 Ground C26 I/O C3 2.5V/3.3V C4 I/O C5 1.5V E24 1.5V E25 No Connect E26 I/O E3 Input E4 Ground F1 1.5V F2 1.5V F23 CYNSE70256 Signal Name Signal Type V 2.5V/3.3V DDQ DQ[24] I/O V Ground SS CFG_L Input V Ground SS SADR[0] Output-T DQ[69] I/O DQ[65] I/O DQ[61] I/O DQ[59] I/O ...
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... Input M3 Ground M4 Output-T N1 2.5V/3.3V N11 Output-T N12 Input N13 Ground N14 Output N15 Ground N16 Ground N2 Ground N23 Ground N24 Ground N25 CYNSE70256 Signal Name Signal Type V 1.5V DD SADR[6] Output-T V 2.5V/3.3V DDQ V 1. Ground SS ID[3] Input ID[4] Input V Ground SS V 1.5V ...
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... W23 Output W24 Ground W25 Ground W26 Ground W3 Ground W4 Ground Y1 Ground Y2 Ground Y23 1.5V Y24 1.5V Y25 Input Y26 Output-T Y3 CYNSE70256 Signal Name Signal Type SADR[18] Output 1.5V DD BHO[0] Output V Ground SS V Ground SS V Ground SS V Ground SS V Ground ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Ball Signal Type Number 1.5V Y4 1.5V No Connect 2.5V/3.3V Ground I/O Voltage Frequency 2.5V/3.3V 2.5V/3.3V 388-ball HSBGA ( 2.33 mm) BH388 CYNSE70256 Signal Name Signal Type V Ground SS Temperature Range 66 MHz Commercial 83 MHz Commercial 51-85102-** Page 108 of 109 ...
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... Document History Page Document Title: CYNSE70256 Network Search Engine Document Number: 38-02035 Issue REV. ECN NO. Date ** 110448 11/29/01 *A 112905 03/22/02 *B 115995 08/27/02 *C 119308 11/22/02 *D 125508 05/08/03 *E 131896 12/12/03 Document #: 38-02035 Rev. *E Orig. of Change AFX New Data Sheet ED Added 3.3V I/O specs. ...