CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 24

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Figure 10-4 shows the timing diagram of a burst Write operation of the data or mask array.
The burst Write operation lasts for (n + 2) CLK cycles. n signifies the number of accesses in the burst as specified in the BLEN
field of the WBURREG register. The following is the block Write operation sequence. This operation assumes that the host ASIC
has programmed the WBURREG of the appropriate bank with the starting ADR and BLEN before initiating a burst Write command.
The CYNSE70256 device writes the data on the DQ[71:0] bus only to the subfield that has the corresponding mask bit set to 1 in
the GMR specified by the index supplied in cycle 1 {CMD[10],CMD[5:3]}. The CYNSE70256 device drives the EOT signal LOW
from cycle 3 to cycle n; the CYNSE70256 device drives the EOT signal HIGH in cycle n + 1 (n is specified in the BLEN field of
the WBURREG).
At the termination of cycle n + 2, the CYNSE70256 device floats the EOT signal to a three-state operation, and a new instruction
can begin.
Table 10-9. Write Address Format for Data and Mask Array (Burst Write)
10.5
In order to write the data and mask arraysof both banks faster for initialization, testing, or diagnostics, many locations can be
written simultaneously in the CYNSE70256 device. When CMD[9] is set in cycles A and B of the Write command during a Write
to the data or mask arrays, the address present on DQ[10:1] that specifies 128 locations in the device is used, and 64 72-bit
locations are simultaneously written in either the data or mask array. Setting DQ[21] to 0 will cause a write to the addresses,
specified by DQ[10:1], closer to address 0, while setting DQ[21] to 1 will cause a write to the addresses, also specified by
DQ[10:1], further from address 0.
Document #: 38-02035 Rev. *E
• Cycle 1A: The host ASIC applies the Write instruction to CMD[1:0] (CMD[2] = 1) using CMDV = 1, and the address supplied
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1, and the address
• Cycle 2: The host ASIC drives the DQ[71:0] with the data to be written to the data or mask array location of the selected
• Cycles 3 to n + 1: The host ASIC drives the DQ[71:0] with the data to be written to the next data or mask array location of
• Cycle n + 2: The CYNSE70256 device drives the EOT signal LOW.
Reserved
Reserved
on the DQ bus as shown in Table 10-9. The host ASIC also supplies the GMR index to mask the Write to the data or mask
array locations in {CMD[10], CMD[5:3]}. The host ASIC sets CMD[9] to 0 for the normal Write.
supplied on the DQ bus. The host ASIC continues to supply the GMR index to mask the Write to the data or mask array
locations in {CMD[10], CMD[5:3]}. The host ASIC selects the device for which ID[4:1] matches the DQ[25:22] lines and the
bank of the device using DQ[21] lines. It selects all devices when DQ[25:21] = 11111.
device. The CYNSE70256 device writes the data from the DQ[71:0] bus only to the subfield with the corresponding mask bit
set to 1 in the GMR that is specified by the index {CMD[10],CMD[5:3]} supplied in cycle 1.
the selected device (addressed by the auto-increment ADR field of the WBURREG register).
[71:26]
DQ
Parallel Write
CMD[10:2]
[25:22]
CMD[1:0]
DQ
ID
ID
CLK2X
PHS_L
CMDV
EOT
DQ
Figure 10-4. BURST Write of the Data and Mask Arrays (BLEN = 4)
0 or 1
0 or 1
Bank
Bank
[21]
DQ
01: Mask array
00: Data array
[20:19]
DQ
Address
cycle
A
Write
1
B
cycle
2
Data0 Data1 Data2 Data3
Reserved
Reserved
[18:16]
DQ
cycle
3
cycle
Do not care
WBURADR, which increments with each access.
Do not care
WBURADR, which increments with each access.
4
cycle
5
. These seventeen bits come from
. These seventeen bits come from
cycle
6
X
[15:0]
DQ
CYNSE70256
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