CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 17

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CYNSE70256-66BHC

Manufacturer Part Number
CYNSE70256-66BHC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYNSE70256-66BHC

Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Package Type
BGA
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant

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Manufacturer
Quantity
Price
Part Number:
CYNSE70256-66BHC
Manufacturer:
TI
Quantity:
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Part Number:
CYNSE70256-66BHC
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7.7
Table 7-6 describes the Write burst address register (WBURREG) fields that must be programmed before a burst Write.
Table 7-6. Write Burst Register Description
7.8
Bit[0] of each 72-bit data entry is specially designated for use in the operation of the Learn command in each of the banks. For
72-bit-configured quadrants, this bit indicates whether a location is full (bit set to 1) or empty (bit set to 0). Every Write and/or
Learn command loads the address of the first 72-bit location that contains a 0 in the entry’s bit[0]. This is stored in the NFA
register(see Table 7-7). If all the bits[0] in a device for both the banks within the device are set to 1, the CYNSE70256 asserts
FULO[1:0] to 1.
For 144-bit-configured quadrants, the LSB of the NFA register is always set to 0. The host ASIC must set both bit[0] and bit[72]
in a 144-bit word to either 0 or 1 to indicate full or empty status. Both bit[0] and bit[72] must be set to either 0 or 1, (that is, the
10 or 01 settings are invalid).
Table 7-7. NFA Register
8.0
The CYNSE70256 device consists of two banks of 64K × 72-bit storage cells referred to as data bits. There is a mask cell
corresponding to each data cell. Figure 8-1 shows the three organizations of the device based on the value of the CFG bits in
the command register.
Document #: 38-02035 Rev. *E
BLEN
Field
ADR
Write Burst Address Register Description
NFA Register
NSE Architecture and Operation Overview
Range
[18:16]
[27:19]
[71:28]
[15:0]
CFG = 0000000000000000
Address
64 K
Figure 8-1. CYNSE70256 Database Width Configuration for Each of the Two Banks
60
Initial Value
72
0
0
32 K
Address
operation from a bank. It automatically increments by one for each successive
Write of the data or mask array. Once the operation is complete, the contents of
this field must be reinitialized for the next operation.
Reserved
Length of Burst Access
locations in a single burst. The BLEN decrements automatically. Once the
operation is complete, the contents of this field must be
reinitialized for the next operation.
Reserved
CFG = 0101010101010101
. This is the starting address of the data or mask array during a burst-Write
.
.
Data
Masks
Reserved
144
71–16
. The device provides the capability to Write from 4–511
16 K
Description
CFG = 1010101010101010
Data
Masks
288
Index
15–0
CYNSE70256
Page 17 of 109

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