K6R4016V1D-UI10 Samsung Semiconductor, K6R4016V1D-UI10 Datasheet - Page 3

• Manufacturer Part Number: K6R4016V1D-UI10
• Manufacturer: Samsung Semiconductor

Specifications of K6R4016V1D-UI10

• Density: 4Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 75mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Compliant

K6R4016V1D
256K x 16 Bit High-Speed CMOS Static RAM
WE
OE
UB
LB
CS
FEATURES
FUNCTIONAL BLOCK DIAGRAM
• Fast Access Time 8,10ns(Max.)
• Low Power Dissipation
• Single 3.3 0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
• Three State Outputs
• 2V Minimum Data Retention: L-Ver. only.
• Center Power/Ground Pin Configuration
• Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16
• Standard Pin Configuration
• Operating in Commercial and Industrial Temperature range.
A
A
A
A
A
A
A
A
A
A
- No Clock or Refresh required
I/O
0
1
2
3
4
5
6
7
8
9
I/O
Standby (TTL)
Operating K6R4016V1D-08 : 80mA(Max.)
1
9
~I/O
~I/O
K6R4016V1D-J : 44-SOJ-400
K6R4016V1D-K : 44-SOJ-400(Lead-Free)
K6R4016V1D-T : 44-TSOP2-400BF
K6R4016V1D-U : 44-TSOP2-400BF (Lead-Free)
K6R4016V1D-E : 48-TBGA with 0.75 Ball pitch
8
16
(CMOS) : 5mA(Max.)
K6R4016V1D-10 : 65mA(Max.)
Clk Gen.
(7mm X 9mm)
: 20mA(Max.)
1.2mA(Max.)L-Ver. only.
Cont.
Cont.
Data
Data
Gen.
CLK
A
10
A
11
Pre-Charge Circuit
256 x 16 Columns
A
Column Select
Memory Array
12
I/O Circuit &
1024 Rows
A
13
A
14
A
15
A
16
A
17
PRELIMPreliminaryPPPPPPPPPINARY
- 3 -
GENERAL DESCRIPTION
The K6R4016V1D is a 4,194,304-bit high-speed Static Random
Access Memory organized as 262,144 words by 16 bits. The
K6R4016V1D uses 16 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. Also it allows that lower and upper
byte access by data byte control(UB, LB). The device is fabri-
cated using SAMSUNG s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The K6R4016V1D is packaged in a 400mil 44-pin plastic SOJ
or TSOP(II) forward or 48 TBGA.
CMOS SRAM
Mar. 2004
Rev 4.0