E28F008SA85 Intel, E28F008SA85 Datasheet
E28F008SA85
Specifications of E28F008SA85
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E28F008SA85 Summary of contents
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... A deep power-down mode lowers power consumption to 1 µW typical through V computing, handheld instrumentation and other low-power applications. The RP# power control input also provides absolute data protection during system power-up/down. Manufactured on Intel ® 0.4 micron ETOX V process technology, the 28F008SA provides the highest levels of quality, reliability and cost-effectiveness. NOTE: This document formerly known as 28F008SA 8-Mbit (1-Mbit x 8) FlashFile™ ...
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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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... Deep Power-Down..................................... 12 3.5 Intelligent Identifier Operation .................... 12 3.6 Write .......................................................... 13 4.0 COMMAND DEFINITIONS............................ 13 4.1Read Array Command ................................ 13 4.2 Intelligent Identifier Command ................... 15 4.3 Read Status Register Command ............... 15 4.4 Clear Status Register Command ............... 15 4.5 Erase Setup/Erase Confirm Commands .... 15 4.6 Erase Suspend/Erase Resume Commands15 4.7 Byte Write Setup/Write Commands .......... 16 5 ...
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... Only devices used after this date must adhere to this new specification. -007 Removed references to reverse pinout throughout document. Added section numbers. Changed document title from 28F008SA 8-Mbit (1-Mbit x 8) FlashFile™ Memory . -008 4 Description Read ...
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... Writing of memory data is performed in byte increments typically within 9 µs—an 80% improvement over current flash memory products. I byte write and block erase currents are typical maximum. V byte write and block PP erase voltage is 11 12.6 V. PRELIMINARY ...
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Figure 1. Block Diagram 6 29042901 PRELIMINARY ...
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Table 1. Pin Descriptions Symbol Type A –A INPUT ADDRESS INPUTS for memory addresses. Addresses are internally 0 19 latched during a write cycle. DQ –DQ INPUT/OUTPUT DATA INPUT/OUTPUTS: Inputs data and commands during CUI 0 7 write cycles; outputs ...
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CE RP ...
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... Figure 4. 28F008SA Array Interface to Intel386SL Microprocessor Superset through PI Bus (Including RY/BY# Masking and Selective Power-Down), for DRAM Backup during System SUSPEND, Resident O/S and Applications and Motherboard Solid-State Disk. PRELIMINARY 28F008SA 29042905 9 ...
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... Interface software to initiate and poll progress of internal byte write and block erase can be stored in any of the 28F008SA blocks. This code is copied to, and executed from, system RAM during actual flash memory update ...
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... PRELIMINARY 3.1 Read The 28F008SA has three read modes. The memory can be read from any of its blocks, and information can be read from the intelligent identifier or status register. V can be at either V PP The first task is to write the appropriate read mode returning command to the CUI (array, intelligent identifier, or status register) ...
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... CPU initialization would the not occur because the flash memory would be providing the status information instead of array data. Intel’s Flash memories allow proper CPU AC initialization following a system reset through the use of the RP# input. In this application RP# is controlled by the same RESET# signal that resets the system CPU ...
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... A read from address 00001H outputs the device code (A2H not necessary to have high voltage applied to V read the intelligent identifiers from the CUI. 3.6 Write Writes to the CUI enable reading of device data and Intelligent Identifiers. They also control inspection and clearing of the status register ...
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... Following the Intelligent Identifier command, two read operations access manufacture and device codes. 5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command. 6. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 14 First Bus Cycle Second Bus Cycle ...
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... Following the command write, a read cycle from address 00000H retrieves the manufacturer code of 89H. A read cycle from address 00001H returns the device code of A2H. To terminate the operation necessary to write another valid command into the register. Like the Read Array command, the Intelligent Identifier command is functional when ...
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... Block erasure repeat of byte write, is required to initialize this data to a known value. 7.0 AUTOMATED BLOCK ERASE As above, the Quick-Erase algorithm of prior Intel Flash devices is now implemented internally, including all preconditioning of block data. WSM operation, erase success and V presence are monitored and reported through RY/BY# and the status register ...
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... DESIGN CONSIDERATIONS 8.1 Three-Line Output Control The 28F008SA will often be used in large memory arrays. Intel provides three control inputs to accommodate multiple memory connections. Three- line control provides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur ...
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Table 4. Status Register Definitions WSMS ESS R.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Erase Suspended 0 = Erase in Progress/Completed SR.5 = ...
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Start Write 20H, Block Address Write D0H, Block Address No Erase Suspend No Suspend WSM Ready? Erase? Yes Yes Full Status Check if Desired Block Erase Completed FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) No SR.3 = ...
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Start Write B0H Write 70H Read Status Register No SR Yes No SR Erase Has Completed Yes Write FFH No Done Reading? Yes Write D0H Continue Erase Figure 7. Erase Suspend/Resume Flowchart 20 Bus Command ...
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Start Write 40H (10H), Byte Address Write Byte Address/Data No WSM Ready? Yes Full Status Check if Desired Byte Write Completed FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error PP Yes ...
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... V Trace on Printed Circuit PP Boards Writing flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the V power supply PP trace. The V pin supplies the memory cell current PP for writing and erasing. Use similar trace widths and layout considerations given to the V power bus ...
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... Sampled, not 100% tested. PRELIMINARY NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. *WARNING: Stressing the device beyond the “Absolute (1) Maximum Ratings” ...
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DC Characteristics Symbol Parameter Notes I Input Load Current LI I Output Leakage LO Current I V Standby Current 1, 3 CCS Deep Power-Down CCD CC Current I V Read Current CCR ...
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DC Characteristics (Continued) Symbol Parameter Notes V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS during Normal PPL PP Operations V V during Erase/Write PPH PP Operations V V ...
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DC Characteristics—Extended Temperature Operation Symbol Parameter Notes I Input Load Current LI I Output Leakage LO Current I V Standby Current 1, 3 CCS Deep Power-Down CCD CC Current I V Read Current CCR CC ...
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DC Characteristics—Extended Temperature Operation Symbol Parameter Notes V Output Low Voltage OL V Output High Voltage OH 1 (TTL) V Output High Voltage OH 2 (CMOS during Normal PPL PP Operations V V during Erase/Write PPH PP ...
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Input Test Points Output 0.8 0.8 0.45 AC test inputs are driven for a Logic “1” OH TTL and V (0. for a Logic “0.” Input timing begins at ...
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AC Characteristics—Read-Only Operations Versions Symbol Parameter Notes t t Read Cycle Time AVAV Address to Output AVQV ACC Delay t t CE# to Output Delay ELQV RP# High to ...
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AC Characteristics—Read-Only Operations Extended Temperature Operation Versions Symbol Parameter t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t CE# to Output Delay ELQV RP# High to Output ...
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Figure 13. AC Waveform for Read Operations PRELIMINARY 28F008SA 29042913 31 ...
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V IH RY/BY# ( RP# ( Figure 14. AC Waveform for Reset Operation # Sym Parameter P1 t RP# Pulse Low Time PLPH (If RP# is tied this specification ...
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AC Characteristics—Write Operations Versions V ± ±10% CC Symbol Parameter Notes t t Write Cycle Time AVAV RP# High PHWL PS Recovery to WE# Going Low t t CE# Setup to ELWL CS WE# ...
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... IN 5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. Byte write and block erase durations are measured to completion (SR RY/BY until determination of byte write/block erase success (SR ...
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... IN 5. The on-chip WSM incorporates all byte write and block erase system functions and overhead of standard Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). ...
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... Block Erase and Byte Write Performance— Extended Temperature Operation Parameter Block Erase Time Block Write Time Byte Write Time NOTES °C, 12 Excludes System-Level Overhead. 3. Contact your Intel representative for information on the maximum byte write specification. 36 Notes 28F008SA-100 (1) Typ Max 2 1 0.6 2.1 8 ...
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Figure 15. AC Waveform for Write Operations PRELIMINARY 28F008SA 29042914 37 ...
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Alternative CE#-Controlled Writes Versions V ± ±10% CC Sym Parameter Notes t t Write Cycle Time AVAV RP# High PHEL PS Recovery to CE# Going Low t t WE# Setup to WLEL WS ...
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NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE#. In systems where CE# defines the write pulsewidth (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be ...
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Alternative CE#-Controlled Writes— Extended Temperature Operation Versions Symbol Parameter t t Write Cycle Time AVAV RP# High Recovery to CE# Going Low PHEL WE# Setup to CE# Going Low WLEL WS t ...
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Figure 16. Alternate AC Waveform for Write Operations PRELIMINARY 28F008SA 29042915 41 ...
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... AP-364 28F008SA Automation and Algorithms Note 3 NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. ...