E28F008SA85 Intel, E28F008SA85 Datasheet - Page 11

• Manufacturer Part Number: E28F008SA85
• Manufacturer: Intel

Specifications of E28F008SA85

• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

2.1
An on-chip state machine controls block erase and
byte write, freeing the system processor for other
tasks. After receiving the Erase Setup and Erase
Confirm commands, the state machine controls
block
progress via the status register and RY/BY# output.
Byte write is similarly controlled, after destination
address and expected data are supplied. The
program and erase algorithms of past Intel
memories are now regulated by the state machine,
including pulse repetition where required and
internal verification and margining of data.
2.2
Depending on the application, the system designer
may choose to make the V
switchable (available only when memory byte
writes/block erases are required) or hardwired to
V
be altered.
provides protection from unwanted byte write or
block erase operations even when high voltage is
applied to V
disabled whenever V
voltage V
28F008SA accommodates either design practice
and encourages optimization of the processor-
memory interface.
The two-step byte write/block erase CUI write
sequence
protection.
3.0
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
PPH
PRELIMINARY
. When V
BUS OPERATION
pre-conditioning
Command User Interface and
Write Automation
Data Protection
LKO
provides
PP
, or when RP# is at V
The 28F008SA CUI
PP
. Additionally, all functions are
= V
CC
PPL
additional
, memory contents cannot
is below the write lockout
and
PP
erase,
software
power supply
architecture
returning
IL
®
. The
Flash
write
3.1
The 28F008SA has three read modes. The memory
can be read from any of its blocks, and information
can be read from the intelligent identifier or status
register. V
The first task is to write the appropriate read mode
command to the CUI (array, intelligent identifier, or
status register). The 28F008SA automatically
resets to read array mode upon initial device power-
up or after exit from deep power-down. The
28F008SA has four control pins, two of which must
be logically active to obtain data at the outputs.
Chip Enable (CE#) is the device selection control,
and when active enables the selected memory
device.
input/output (DQ
active drives data from the selected memory onto
the I/O bus. RP# and WE# must also be at V
Figure 13 illustrates read bus cycle waveforms.
3.2
With OE# at a logic-high level (V
outputs are disabled. Output pins (DQ
placed in a high-impedance state.
3.3
CE# at a logic-high level (V
28F008SA in standby mode. Standby operation
disables much of the 28F008SA’s circuitry and
substantially reduces device power consumption.
The outputs (DQ
impedance state independent of the status of OE#.
If the 28F008SA is deselected during block erase or
byte write, the device will continue functioning and
consuming normal active power until the operation
completes.
Read
Output Disable
Standby
Output
PP
can be at either V
0
–DQ
0
Enable
–DQ
7
) direction control, and when
7
) are placed in a high-
(OE#)
PPL
or V
IH
IH
) places the
is
), the device
28F008SA
PPH
0
–DQ
the
.
7
) are
data
11
IH
.