STA333BW STMicroelectronics, STA333BW Datasheet - Page 40

• Manufacturer Part Number: STA333BW
• Manufacturer: STMicroelectronics

Specifications of STA333BW

• Operational Class: Class-AB
• Audio Amplifier Output Configuration: 1-Channel Mono/2-Channel Stereo
• Audio Amplifier Function: Speaker
• Total Harmonic Distortion: 0.2@8Ohm@1W%
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): 3.3/5/9/12/15/18V
• Power Supply Requirement: Quad
• Rail/rail I/o Type: No
• Power Supply Rejection Ratio: 80dB
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): 2.7/4.5V
• Dual Supply Voltage (max): 3.6/21.5V
• Operating Temp Range: -20C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Package Type: PowerSSO EP
• Lead Free Status / Rohs Status: Compliant

Register description
6.2
40/67
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power-stage, then the master clock to all internal hardware expect the
I
External amplifier power down
Table 49.
The EAPD register directly disables / enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled). This
register also controls the FFX4B / EAPD output pin when OCFG = 10.
Volume control registers (addr 0x06 - 0x0A)
The volume structure of the STA333BW consists of individual volume registers for each
channel and a master volume register that provides an offset to each channels volume
setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB
to -80 dB.
As an example if C3VOL = 0x00 or +48 dB and MVOL = 0x18 or -12 dB, then the total gain
for channel 3 = +36 dB.
The channel mutes provide a “soft mute” with the volume ramping down to mute in
4096 samples from the maximum volume setting at the internal processing rate
(approximately 96 kHz).
A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) in any
channel volume register. When volume offsets are provided via the master volume register
any channel whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1
(addr
transitions. When ZCE = 0, volume updates occur immediately.
2
7
C block is gated. This places the IC in a very low power consumption state.
Bit
0x04)) on a per channel basis as this creates the smoothest possible volume
R/W
R/W
External amplifier power down
0
RST
EAPD
Doc ID 13773 Rev 3
Name
0: external power stage power down active
1: normal operation
Description
(Configuration register E
STA333BW