H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 67

58T1898

H5TQ2G63BFR-H9C

Manufacturer Part Number
H5TQ2G63BFR-H9C
Description
58T1898
Manufacturer
HYNIX SEMICONDUCTOR
Datasheet

Specifications of H5TQ2G63BFR-H9C

Memory Type
SDRAM
Memory Configuration
128M X 16
Access Time
13.5ns
Interface Type
CMOS
Memory Case Style
FBGA
No. Of Pins
96
Operating Temperature Range
0°C To +85°C
Memory Size
2 Gbit
Rohs Compliant
Yes

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Rev. 0.5 / Aug. 2010
10. Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
800MHz Speed Bins
For specific Notes See “11. Electrical Characteristics and AC Timing” on page 71.
Internal read command
ACT to internal read or
ACT to PRE command
CL = 10
CL = 11
PRE command period
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
ACT to ACT or REF
command period
write delay time
Supported CWL Settings
Supported CL Settings
to first data
Parameter
period
CWL = 5,6,7 t
CWL = 6, 7
CWL = 5, 6
CWL = 5,6
Speed Bin
CWL = 5
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 7
CWL = 8
CWL = 7
CWL = 8
CWL = 8
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
t
t
RCD
t
t
t
RAS
AA
RP
RC
51.25
1.875
1.875
12.5
37.5
1.25
1.25
min
2.5
2.5
1.5
1.5
15
15
5,6, 7,8, 9,10,11
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
800MHz
5, 6, 7,8
9 * tREFI
1.875
1.875
max
3.3
3.3
2.5
2.5
1.5
1.5
20
Unit
n
n
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
H5TQ2G63BFR
1,2,3,4,6
1,2,3,4,6
1,2,3,4,6
1,2,3,4,6
1,2,3,4,6
1,2,3,6
1,2,3,6
1,2,3,6
1,2,3,4
1,2,3,4
Note
4
4
4
4
4
4
4
4
4
4
67

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