SPD6729QCE Intel, SPD6729QCE Datasheet - Page 88

• Manufacturer Part Number: SPD6729QCE
• Description: PCI To PC Card (PCMCIA) Controller 208-Pin MQFP
• Manufacturer: Intel

Specifications of SPD6729QCE

• Package: 208MQFP
• Operating Temperature: 0 to 70 °C

PD6729 — PCI-to-PC Card (PCMCIA) Controller
11.2
88
Register Name: Command Timing 0-1
Index: 3Bh, 3Eh
NOTE:
1. Timing set 0 (index 3Bh) resets to 5h, providing a 300-ns nominal PC card command width useable for support of ‘250-ns’ PC
Command Prescalar Select
cards. Timing set 1 (3Eh) resets to 14h, providing a 900 ns nominal PC card command width.
Bit
7
RW:00
Bits 7-6: Setup Prescalar Select
This field chooses one of four prescalar values N
Multiplier Value (bits 5-0) to control the length of setup time before a command becomes active.
Command Timing 0-1
There are two separate Command Timing registers, each with identical fields. These registers are
located at the following indexes:
The Command Timing register for each timer set controls how long a PCMCIA cycle’s command
(that is, -OE, -WE, -IORD, -IOWR; see
number of internal clock cycles.
The overall command timing length C is programmed by selecting a 2-bit prescaling value (bits 7-6
of this register) representing weights of 1, 16, 256, or 4096, and then selecting a multiplier value
(bits 5-0) to which that prescalar is multiplied to produce the overall command timing length
according to the following formula:
The value of C, representing the number of clock cycles for a command, is then multiplied by the
clock period of the internal clock driving the PC card interface to determine the actual command
active time (see
00
01
10
11
Bit
6
Index
3Bh
3Eh
N pres = 1
N pres = 16
N pres = 256
N pres = 4096
“PCMCIA Bus Timing Calculations” on page 101
Bit
(Socket A)Command Timing
Command Timing 0
Command Timing 1
C = (N
5
pres
N
Bit
val
4
)
1
Table 2 on page
Command Multiplier Value
Bit
RW:000101/010100
pres
3
that are combined with the value of the Setup
18) active time will be, in terms of the
Bit
2
1
for further discussion).
Register Compatibility Type: 365
Bit
1
Register Per: socket
Datasheet
Bit
0