MACH120-15JC Lattice, MACH120-15JC Datasheet - Page 20

• Manufacturer Part Number: MACH120-15JC
• Description: CPLD MACH 1 Family 48 Macro Cells 66.6MHz EECMOS Technology 5V 68-Pin PLCC
• Manufacturer: Lattice

Specifications of MACH120-15JC

• Package: 68PLCC
• Family Name: MACH 1
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 48
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 12
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic
polarity. This feature provides extra flexibility to the designer and is especially valuable in sim-
plifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways V
to its steady state, two conditions are required to insure a valid power-up reset. These conditions
are:
1. The V
2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback
Parameter
Symbol
setup times are met.
t
t
WL
PR
t
S
Registered
CC
rise must be monotonic.
Output
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
Power
Clock
4 V
Parameter Descriptions
Power-Up Reset Waveform
MACH120-12/15
t
PR
t
WL
t
S
See
Switching
Characteristics
Max
10
CC
V
14129J-16
CC
can rise
Unit
s
21