723631L15PF Integrated Device Technology (Idt), 723631L15PF Datasheet

723631L15PF

Manufacturer Part Number

723631L15PF

Description

FIFO Mem Sync Dual Depth Bi-Dir 512 x 36 120-Pin TQFP

Manufacturer

Integrated Device Technology (Idt)

Datasheet

1.IDT723631L20PF8.pdf (21 pages)

Specifications of 723631L15PF

Package

120TQFP

Configuration

Dual

Bus Directional

Bi-Directional

Density

18 Kb

Organization

512x36

Data Bus Width

36 Bit

Timing Type

Synchronous

Expansion Type

Depth

Typical Operating Supply Voltage

5 V

Operating Temperature

0 to 70 Â°C

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FEATURES:

• • • • •

FUNCTIONAL BLOCK DIAGRAM

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

CLKA

W/RA

Storage capacity:

Supports clock frequencies up to 67 MHz

Fast access times of 11ns

Free-running CLKA and CLKB can be asynchronous or coinci-

dent (permits simultaneous reading and writing of data on a

single clock edge)

Clocked FIFO buffering data from Port A to Port B

Synchronous read retransmit capability

Mailbox register in each direction

Programmable Almost-Full and Almost-Empty flags

Microprocessor interface control logic

Input Ready (IR) and Almost-Full (AF) flags synchronized by

CLKA

MBA

CSA

ENA

MBF2

RST

/SEN

IDT723631 - 512 x 36

IDT723641 - 1,024 x 36

IDT723651 - 2,048 x 36

- A

/SD

Control

Port-A

Logic

Reset

Logic

CMOS SyncFIFO™

512 x 36

1,024 x 36

2,048 x 36

Pointer

Write

Flag Offset

Status Flag

Registers

RAM ARRAY

1,024 x 36

2,048 x 36

512 x 36

Mail 2

Mail 1

Logic

Pointer

Read

• • • • •

DESCRIPTION:

CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz

and has read access times as fast as 12ns. The 512/1,024/2,048 x 36

dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory

has retransmit capability, which allows previously read data to be ac-

cessed again. The FIFO has flags to indicate empty and full conditions and

two programmable flags (Almost-Full and Almost-Empty) to indicate when a

selected number of words is stored in memory. Communication between

each port may take place with two 36-bit mailbox registers. Each mailbox

Output Ready (OR) and Almost-Empty (AE) flags synchronized

by CLKB

Available in 132-pin plastic quad flat package (PQFP) or space-

saving 120-pin thin quad flat package (TQFP)

Industrial temperature range (–40°C to +85°C) is available

Green parts available, see ordering information

The IDT723631/723641/723651 is a monolithic high-speed, low-power,

FEBRUARY 2009

Control

Port-B

Logic

MBF1

RTM

RFM

- B

IDT723631

IDT723641

IDT723651

3023 drw01

DSC-2023/7

CLKB

CSB

W/RB

ENB

MBB

Related parts for 723631L15PF

723631L15PF Summary of contents

Page 1

CMOS SyncFIFO™ 512 x 36 1,024 x 36 2,048 x 36 FEATURES: • • • • • Storage capacity: IDT723631 - 512 x 36 IDT723641 - 1,024 x 36 IDT723651 - 2,048 x 36 • • • • • Supports ...

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 DESCRIPTION (CONTINUED) register has a flag to signal when new mail has been stored. Two or more devices may be used in parallel to create wider data ...

Page 3

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 PIN CONFIGURATION (CONTINUED GND 8 A ...

Page 4

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 PIN DESCRIPTION Symbol Name I/O A0-A35 Port-A Data I/O 36-bit bidirectional data port for side A. AE Almost-Empty O Programmable flag synchronized to CLKB LOW ...

Page 5

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I (2) V Output Voltage ...

Page 6

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 250 f = 1/2 f data T = 25° 0pF L 200 150 100 Figure 1. Typical Characteristics: Supply vs ...

Page 7

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Commercial 5.0V ± 10 0°C to +70°C; Industrial ...

Page 8

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 ELECTRICAL CHARACTERISTICS (Commercial 5.0V ± 10 0°C to +70°C; Industrial Symbol Parameter f Clock Frequency, CLKA or CLKB S ...

Page 9

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 SIGNAL DESCRIPTION RESET The IDT723631/723641/723651 is reset by taking the Reset (RST) input LOW for at least four port-A Clock (CLKA) and four port-B (CLKB) LOW-to-HIGH transitions. ...

Page 10

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 when CLKA and CLKB operate asynchronously to one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA. Table 4 shows the ...

Page 11

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 grammed from port A, or programmed serially (see Almost-Empty flag and Almost-Full flag offset programming above). The AE flag is LOW when the FIFO contains X or ...

Page 12

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 When the FIFO is in retransmit mode and RFM is HIGH, a rising CLKB edge loads the current read pointer with the shadow read-pointer value and the ...

Page 13

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 CLKA CLKB t RSTS RST FS1,FS0 RSF AE t RSF AF t RSF MBF1, MBF2 Figure 2. FIFO Reset Loading X and Y with ...

Page 14

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 CLKA 4 RST IR t FSS FS1/SEN t t FSH FSS FS0/SD NOTE not necessary to program Offset register bits on consecutive clock cycles. ...

Page 15

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 CLKA CSA LOW W/RA HIGH t t ENS2 ENH2 MBA t t ENS1 ENH1 ENA IR HIGH A35 t SKEW1 ...

Page 16

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS1 ENB HIGH OR B0 -B35 Previous Word in FIFO Output Register CLKA ...

Page 17

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 CLKA t t ENH1 ENS1 ENA t PAF (2) AF [Depth -(Y+1)] Words in FIFO CLKB ENB NOTES: is the minimum time between a rising CLKA edge ...

Page 18

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 CLKA FIFO Filled to First Restransmit Word IR CLKB t RMS RTM NOTE the minimum time between a rising CLKB edge and a rising ...

Page 19

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 CLKB t ENS2 CSB t ENS2 W/RB t ENS2 MBB t ENS2 ENB B0 - B35 CLKA MBF2 CSA W/RA MBA ENA A35 ...

Page 20

IDT723631/723641/723651 CMOS SyncFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5 ...

Page 21

ORDERING INFORMATION XXXXX X XX Device Type Power Speed Package NOTES: 1. Industrial temperature range product for 20ns is available as a standard device. 2. Green parts are available, for specific speeds and packages contact your sales office. DATASHEET DOCUMENT ...

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