723631L15PF Integrated Device Technology (Idt), 723631L15PF Datasheet - Page 13

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723631L15PF

Manufacturer Part Number
723631L15PF
Description
FIFO Mem Sync Dual Depth Bi-Dir 512 x 36 120-Pin TQFP
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 723631L15PF

Package
120TQFP
Configuration
Dual
Bus Directional
Bi-Directional
Density
18 Kb
Organization
512x36
Data Bus Width
36 Bit
Timing Type
Synchronous
Expansion Type
Depth
Typical Operating Supply Voltage
5 V
Operating Temperature
0 to 70 °C
NOTE:
1. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.
FS1,FS0
FS1,FS0
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
A0 - A35
CLKA
MBF1,
MBF2
CLKB
CLKA
ENA
RST
RST
IR
AE
OR
AF
IR
t
FSS
4
Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values from Port A
t
RSTS
t
FSH
t
t
t
RSF
RSF
RSF
Figure 2. FIFO Reset Loading X and Y with a Preset Value of Eight
t
PIR
t
PIR
13
t
DS
t
POR
AF Offset
t
FSS
(Y)
t
DH
0,1
t
t
ENS1
RSTH
AE Offset
t
FSH
(X)
t
ENH1
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
First Word
Stored in FIFO
t
PIR
3023 drw05
3023 drw06

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