723631L15PF Integrated Device Technology (Idt), 723631L15PF Datasheet - Page 12

• Manufacturer Part Number: 723631L15PF
• Description: FIFO Mem Sync Dual Depth Bi-Dir 512 x 36 120-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723631L15PF

• Package: 120TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 512x36
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

edge loads the current read pointer with the shadow read-pointer value
and the OR flag reflects the new level of fill immediately. If the retransmit
changes the FIFO status out of the almost-empty range, up to two CLKB
rising edges after the retransmit cycle are needed to switch AE high (see
Figure 12). The rising CLKB edge that takes the FIFO out of retransmit
mode shifts the read pointer used by the IR and AF flags from the shadow
to the current read pointer. If the change of read pointer used by IR and
AF should cause one or both flags to transmit HIGH, at least two CLKA
synchronizing cycles are needed before the flags reflect the change. A
rising CLKA edge after the FIFO is taken out of retransmit mode is the first
synchronizing cycle of IR if it occurs at time t
rising CLKB edge (see Figure 13). A rising CLKA edge after the FIFO is
taken out of retransmit mode is the first synchronizing cycle of AF if it occurs
at time t
MAILBOX REGISTERS
pass command and control information between port A and port B. The
Mailbox select (MBA, MBB) inputs choose between a mail register and a
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
When the FIFO is in retransmit mode and RFM is HIGH, a rising CLKB
Two 36-bit bypass registers are on the IDT723631/723641/723651 to
SKEW2
or greater after the rising CLKB edge (see Figure 14).
SKEW1
or greater after the
12
FIFO for a port data transfer operation. A LOW-to-HIGH transition on
CLKA writes A0-A35 data to the mail1 register when a port-A Write is
selected by CSA, W/RA, and ENA with MBA HIGH. A LOW-to-HIGH
transition on CLKB writes B0-B35 data to the mail2 register when a port-B
Write is selected by CSB, W/RB, and ENB with MBB HIGH. Writing data to
a mail register sets its corresponding flag (MBF1 or MBF2) LOW.
Attempted writes to a mail register are ignored while its mail flag is LOW.
comes from the FIFO output register when the port-B Mailbox select (MBB)
input is LOW and from the Mail1 register when MBB is HIGH. Mail2 data is
always present on the port-A data (A0-A35) outputs when they are active.
The Mail1 register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition
on CLKB when a port-B Read is selected by CSB, W/RB, and ENB with
MBB HIGH. The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-
HIGH transition on CLKA when a port-A Read is selected by CSA, W/RA,
and ENA with MBA HIGH. The data in a mail register remains intact after it
is read and changes only when new data is written to the register. Mail
Register and Mail Register Flag timing can be found in Figure 15
and 16.
When the port-B data (B0-B35) outputs are active, the data on the bus
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES