723631L15PF Integrated Device Technology (Idt), 723631L15PF Datasheet - Page 4

• Manufacturer Part Number: 723631L15PF
• Description: FIFO Mem Sync Dual Depth Bi-Dir 512 x 36 120-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723631L15PF

• Package: 120TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 512x36
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

PIN DESCRIPTION
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
Symbol
A0-A35
AE
AF
B0-B35
CLKA
CLKB
CSA
CSB
ENA
ENB
FS1/
SEN,
FS0/SD
IR
MBA
MBB
MBF1
MBF2
OR
RFM
RST
RTM
W/RA
W/RB
Name
Port-A Data
Almost-Empty
Flag
Almost-Full
Flag
Port-B Data
Port-A Clock
Port-B Clock
Port-A Chip
Select
Port-B Chip
Select
Port-A Enable
Port-B Enable
Flag-Offset
Select 1/
Serial Enable
Flag Offset 0/
Serial Data
Input Ready
Flag
Port-A Mailbox
Select
Port-B Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
Output Ready
Flag
Read From
Mark
Reset
Retransmit
Mode
Port-A Write/
Read Select
Port-B Write/
Read Select
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
36-bit bidirectional data port for side A.
Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to the value in
the Almost-Empty register (X).
Programmable flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO is less than or equal to the
value in the Almost-Full Offset register (Y).
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port-A and may be asynchronous or coincident to CLKB.
IR and AF are synchronous to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port-B and may be asynchronous or coincident to CLKA.
OR and AE are synchronous to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35 outputs are in the
high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35 outputs are in the
high-impedance state when CSB is HIGH.
FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During a device reset, FS1/SEN and
FS0/SD selects the flag offset programming method. Three Offset register programming methods are available: automatically
load one of two preset values, parallel load from port A, and serial load.
When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to the LOW-to-
HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into the X and Y
registers. The number of bit writes required to program the Offset registers is 18/20/22. The first bit write stores the Y-register
MSB and the last bit write stores the X-register LSB.
IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW, the FIFO is full and writes to its array are
disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the retransmit
data and prevents further writes. IR is set LOW during reset and is set HIGH after reset.
A HIGH level chooses a mailbox register for a port-A read or write operation.
A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active, a HIGH
level on MBB selects data from the mail1 register for output and a LOW level selects FIFO data for output.
MBF1 is set LOW by the LOW-to-HIGH transition of CLKA that writes data to the mail1 register. MBF1 is set HIGH by a
LOW-to-HIGH transition of CLKB when a port-B readis selected and MBB is HIGH. MBF1 is set HIGH by a reset.
MBF2 is set LOW by the LOW-to-HIGH transition of CLKB that writes data to the mail2 register. MBF2 is set HIGH by a
LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH by a reset.
OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is LOW, the FIFO is empty and reads are disabled.
Ready data is present in the output register of the FIFO when OR is HIGH. OR is forced LOW during the reset and goes
HIGH on the third LOW-to-HIGH transition of CLKB after a word is loaded to empty memory.
When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-to-HIGH transition of CLKB to reset the read pointer
to the beginning retransmit location and output the first selected retransmit data.
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST
is LOW. The LOW-to-HIGH transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.
When RTM is HIGH and valid data is present in the FIFO output register (OR is HIGH), a LOW-to-HIGH transition of CLKB
selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word remains the initial
retransmit point until a LOW- to-HIGH transition of CLKB occurs while RTM is LOW, taking the FIFO out of retransmit mode.
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The
A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The
B0-B35 outputs are in the high-impedance state when W/RB is LOW.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
4
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES