ST52T440F3M6 STMicroelectronics, ST52T440F3M6 Datasheet - Page 54

• Manufacturer Part Number: ST52T440F3M6
• Description: MCU 8-Bit ST52 CISC 8KB EPROM 5V 20-Pin SO
• Manufacturer: STMicroelectronics

Specifications of ST52T440F3M6

• Package: 20SO
• Family Name: ST52
• Maximum Speed: 20 MHz
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 13
• On-chip Adc: 6-chx12-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 1

ST52T400/T440/E440/T441
8 WATCHDOG TIMER
8.1 Functional Description
The Watchdog Timer (WDT) is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which causes the application program
to abandon its normal sequence. The WDT circuit
generates an MCU reset on expiry of a pro-
grammed time period (Timeout), unless the pro-
gram refreshes the WDT before the end of the
programmed time period itself.
16 different time delays can be selected by using
the WDT configuration register REG_CONF2 as
in Table 8.2.
WDT is activated by the assembler instruction
WDTRFR.
At the end of the programmed time delay, WDT
starts a reset cycle pulling the reset pin low.
During normal operation, when WDT is active, the
application program has to refresh this peripheral
at regular intervals to prevent an MCU reset. WDT
refresh is performed by the WDTRFR assembler
instruction.
To stop WDT during the user program executions
instruction WDTSLP has to be used.
WDT working frequency is equal to Master Clock
Figure 8.1 Watchdog Block Diagram
54/94
PRES CLK = CLK MASTER
WDTRFR
RESET
WDTSLP
REG_CONF 2
PRESCALER
D3
D2
D1
frequency divided by a fixed Prescaler with a divi-
sion factor of 500, to obtain WDT CLK signal that
is used to fix the WDT Timeout period (Figure
8.1).
Table 8.1 Watchdog Timing range (CLKM=20
With a Master Clock of 20MHz, for instance, a
WDT Timeout period can be defined between
0.025ms and 234.375ms, depending on WDT
REG_CONF2 values.
Timeout delay values at different Master Clock fre-
quencies can be calculated as the product of WDT
clock number pulses (Table 8.2) by WDT CLK
period (Table 8.4).
Warning: changing the REG_CONF2 value when
the WDT is active, a WDT reset is generated and
the CPU is restarted. To avoid this side effect, use
the WDTSLP instruction before changing the
REG_CONF2.
D0
max
min
WTD CLK
MHz)
GENERATOR
WDT Timeout period (ms)
RESET
WDT
234.375
0.025
RESET