AD7609BSTZ Analog Devices Inc, AD7609BSTZ Datasheet - Page 26

• Manufacturer Part Number: AD7609BSTZ
• Description: 58T8900
• Manufacturer: Analog Devices Inc

Specifications of AD7609BSTZ

• Resolution (bits): 18bit
• Sampling Rate: 250kSPS
• Input Channel Type: Differential
• Data Interface: Serial, SPI
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Rohs Compliant: Yes

AD7609
DIGITAL INTERFACE
The
and a high speed serial interface. The required interface mode is
selected via the PAR /SER SEL pin.
The operation of the interface modes is described in the
following sections.
PARALLEL INTERFACE (PAR/SER SEL = 0)
Data can be read from the
standard CS and RD signals. To read the data over the parallel
bus, the PAR /SER SEL pin should be tied low. The CS and RD
input signals are internally gated to enable the conversion result
onto the data bus. The data lines, DB15 to DB0, leave their high
impedance state when both CS and RD are logic low.
The rising edge of the CS input signal three-states the bus and
the falling edge of the CS input signal takes the bus out of the
high impedance state. CS is the control signal that enables the
data lines; it is the function that allows multiple
devices to share the same parallel data bus. The
be permanently tied low, and the RD signal can be used to
access the conversion results, as shown in
operation of new data can take place after the BUSY signal
goes low (
from the previous conversion process can take place while
BUSY is high (
The RD pin is used to read data from the output conversion
results register. Two RD pulses are required to read the full
18-bit conversion result from each channel. Applying a
sequence of 16 RD pulses to the
conversion results out from each channel onto the parallel
output bus, DB[15:0], in ascending order. The first RD falling
edge after BUSY goes low clocks out DB[17:2] of the V1 result,
the next RD falling edge updates the bus with DB[1:0] of the V1
result. It takes 16 RD pulses to read the eight 18-bit conversion
results from the AD7609. The 16
the DB[1:0] conversion result for Channel V8. When the RD
signal is logic low, it enables the data conversion result from
each channel to be transferred to the digital host (DSP, FPGA).
When there is only one
does not share the parallel bus, data can be read using only one
control signal from the digital host. The CS and RD signals
can be tied together, as shown in
bus comes out of three-state on the falling edge of
combined CS and RD signal allows the data to be clocked out
of the
CS is used to frame the data transfer of each data channel and
16 CS pulses are required to read the eight channels of data.
AD7609
AD7609
Figure 2
provides two interface options: a parallel interface
Figure 3
and to be read by the digital host. In this case,
), or, alternatively, a read operation of data
).
AD7609
AD7609
AD7609
th
in a system/board and it
Figure 5
falling edge of RD clocks out
via the parallel data bus with
RD pin clocks the
. In this case, the data
Figure 4
CS signal can
AD7609
. A read
CS / RD . The
Rev. 0 | Page 26 of 36
SERIAL INTERFACE (PAR/SER SEL = 1)
To read data back from the
the PAR /SER SEL pin should be tied high. The CS and SCLK
signals are used to transfer data from the AD7609. The
has two serial data output pins, D
read back from the
lines. For the
Channel V4 first appear on D
from Channel V5 to Channel V8 first appear on D
The CS falling edge takes the data output lines (D
D
sion result. The rising edge of SCLK clocks all subsequent data
bits onto the serial data outputs, D
input can be held low for the entire serial read or it can be
pulsed to frame each channel read of 18 SCLK cycles.
Figure 44 shows a read of eight simultaneous conversion results
using two D
transfer is used to access data from the
low to frame the entire 72 SCLK cycles. Data can also be clocked
out using only one D
mended to access all conversion data, because the channel data
is output in ascending order. For the
conversion results on one D
are required. These 144 SCLK cycles can be framed by one
signal or each group of 18 SCLK cycles can be individually
framed by the CS signal. The disadvantage of using only one
D
conversion. The unused D
in serial mode. For the AD7609, if D
single D
order: V5, V6, V7, V8, V1, V2, V3, V4; however, the FRSTDATA
indicator returns low after V5 is read on D
Figure 43.
OUT
OUT
B) out of three-state and clocks out the MSB of the conver-
line is that the throughput rate is reduced if reading after
OUT
AD7609
line, the channel results are output in the following
OUT
AD7609
Interface Diagram: One
lines on the AD7609. In this case, a 72 SCLK
AD7609
DB[15:0]
AD7609
OUT
BUSY
and RD Shorted Together
, conversion results from Channel V1 to
CS
RD
line, in which case D
OUT
14
13
12
33:16
AD7609
OUT
using one or both of these D
OUT
line should be left unconnected
INTERRUPT
line, a total of 144 SCLK cycles
A, whereas conversion results
OUT
OUT
AD7609
over the serial interface,
A and D
OUT
AD7609
A and D
AD7609
B is to be used as a
DIGITAL
HOST
OUT
Using the Parallel Bus; CS
OUT
OUT
B.
to access all eight
OUT
B. Data can be
and CS is held
A is recom-
B. The CS
OUT
OUT
A and
B.
AD7609
OUT
CS