MT46H64M16LFCK-6:ATR Micron Technology Inc, MT46H64M16LFCK-6:ATR Datasheet - Page 27

• Manufacturer Part Number: MT46H64M16LFCK-6:ATR
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H64M16LFCK-6:ATR

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 14b
• Access Time (max): 6.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 115mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
12.
13. Referenced to each output group: for x16, LDQS with DQ[7:0]; and UDQS with DQ[15:8].
14. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/
15. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and ad-
16. These parameters guarantee device timing but are not tested on each device.
17. The valid data window is derived by achieving other specifications:
18.
19.
20.
21. Fast command/address input slew rate ≥1 V/ns. Slow command/address input slew rate
22. READs and WRITEs with auto precharge must not be issued until
23. The refresh period equals 64ms. This equates to an average refresh rate of 7.8125μs.
24. This is not a device limit. The device will operate with a negative value, but system per-
25. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command.
26. The maximum limit for this parameter is not a device limit. The device will operate with
27. At least 1 clock cycle is required during
28. Clock must be toggled a minimum of two times during the
t
next highest integer.
For x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with
DQ[31:24].
DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to
and
tionality is uncertain.
dresses) are measured between V
V
and
duty cycle and a practical data valid window can be derived. The clock is provided a max-
imum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a
45/55 ratio.
t
CK# inputs, collectively.
t
These parameters are not referenced to a specific voltage level, but specify when the
device output is no longer driving (
t
≥0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated:
tional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns.
added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is
uncertain.
fied prior to the internal PRECHARGE command being issued.
formance could be degraded due to bus turnaround.
The case shown (DQS going from High-Z to logic low) applies when no WRITEs were pre-
viously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH
during this time, depending on
a greater value for this parameter, but system performance (bus turnaround) will de-
grade accordingly.
DAL = (
HP (MIN) is the lesser of
HZ and
HZ (MAX) will prevail over
IL(AC)
t
t
DH for each 100 mV/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, func-
QH (
for falling input signals.
t
t
WR/
LZ transitions occur in the same access time windows as valid data transitions.
t
HP -
t
CK) + (
Electrical Specifications – AC Operating Conditions
t
QHS). The data valid window derates directly proportional with the clock
t
RP/
t
CK): for each term, if not already an integer, round up to the
t
CL (MIN) and
27
t
DQSCK (MAX) +
t
DQSS.
IL(DC)
1Gb: x16, x32 Mobile LPDDR SDRAM
t
HZ) or begins driving (
Micron Technology, Inc. reserves the right to change products or specifications without notice.
to V
t
t
CH (MIN) actually applied to the device CK and
WR time when in auto precharge mode.
IH(AC)
t
RPST (MAX) condition.
for rising input signals and V
t
LZ).
t
XSR period.
© 2007 Micron Technology, Inc. All rights reserved.
t
RAS (MIN) can be satis-
t
HP (
t
IS has an addi-
t
t
CK/2),
IH has 0ps
IH(DC)
t
DQSQ,
to
t
DS