IDT82P2816BBG IDT, Integrated Device Technology Inc, IDT82P2816BBG Datasheet - Page 90

• Manufacturer Part Number: IDT82P2816BBG
• Description: IC LINE INTERFACE UNIT 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BBG

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1702; 82P2816BBG

RCF1 - Receive Configuration Register 1
Address: 00BH, 04BH, 08BH, 0CBH, 10BH, 14BH, 18BH, 1CBH, (CH1~CH8)
Type: Read / Write
Default Value: 01H
Programming Information
IDT82P2816
RMF_DEF2
7 - 5
1 - 0
Bit
4
3
2
20BH, 24BH, 28BH, 2CBH, 30BH, 34BH, 38BH, 3CBH, (CH9~CH16)
7CBH (CH0)
7
RMF_DEF[2:0] These bits are valid only in Receive Single Rail NRZ Format mode and Receive Dual Rail Sliced mode. They determine the out-
R_MD[1:0]
R_CODE
RCK_ES
RD_INV
Name
RMF_DEF1
6
put on the RMFn pin.
000: PRBS/ARB indication when the PRBS/ARB detection is switched to the receive path. Or reserved when the PRBS/ARB
detection is switched to the transmit path. (default)
001: LAIS indication.
010: XOR data of positive and negative sliced data.
011: Recovered clock (RCLK).
100: LEXZ indication.
101: LBPV indication.
110: LEXZ + LBPV indication.
111: LLOS indication.
This bit selects the active edge of the RCLKn pin.
0: Rising edge. (default)
1: Falling edge.
This bit determines the active level on the RDn, RDPn and RDNn pins.
0: Active high. (default)
1: Active low.
This bit selects the line code rule for the receive path.
0: B8ZS (in T1/J1 mode) / HDB3 (in E1 mode). (default)
1: AMI.
These bits determines the receive system interface.
00: Receive Single Rail NRZ Format system interface. The data is output on RDn in NRZ format and a 1.544 MHz (in T1/J1
mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn.
01: Receive Dual Rail NRZ Format system interface. The data is output on RDPn and RDNn in NRZ format and a 1.544 MHz (in
T1/J1 mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn. (default)
10: Receive Dual Rail RZ Format system interface. The data is output on RDPn and RDNn in RZ format and a 1.544 MHz (in T1/
J1 mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn.
11: Receive Dual Rail Sliced system interface. The data is output on RDPn and RDNn in RZ format directly after passing through
the Slicer.
RMF_DEF0
5
RCK_ES
4
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
90
RD_INV
3
Description
R_CODE
2
R_MD1
1
February 6, 2009
R_MD0
0