HC55140IMZ Intersil, HC55140IMZ Datasheet - Page 13

• Manufacturer Part Number: HC55140IMZ
• Description: IC SLIC UNIVERSAL LP 28-PLCC
• Manufacturer: Intersil
• Series: UniSLIC14r

Specifications of HC55140IMZ

• Function: Subscriber Line Interface Concept (SLIC)
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 2.25mA
• Power (watts): 1.5W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Includes: Battery Tracking Anti-Clipping, Loop and Ground Key Detection, Ring Control
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -

Notes
10. Metallic to Longitudinal Balance - The metallic to longitudinal
11. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal
12. Two-Wire Return Loss - The 2-wire return loss is computed
13. Overload Level (4-Wire Port Off-Hook) - The overload level
2. Overload Level (Two-Wire Port, Off Hook) - The overload
3. Overload Level (Two-Wire Port, On Hook) - The overload
4. Longitudinal Impedance - The longitudinal impedance is
5. Longitudinal Current Limit (On-Hook Active) - On-Hook
6. Longitudinal Current Limit (Off-Hook Active) - Off-Hook
7. Longitudinal to Metallic Balance - The longitudinal to
8. Metallic to Longitudinal FCC Part 68, Para 68.310 - The
9. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire
level is specified at the 2-wire port (V
the 4-wire receive port (E
Increase the amplitude of E
Reference Figure 1.
level is specified at the 2-wire port (V
the 4-wire receive port (E
the amplitude of E
Reference Figure 1.
computed using the following equations, where TIP and RING
voltages are referenced to ground. L
A
(TIP) L
(RING) L
where: E
longitudinal current limit is determined by increasing the (60Hz)
amplitude of E
is greater than 28mA RMS /Wire. Under this condition, SHD pin
remains low (no false detection) and the 2-wire to 4-wire
longitudinal balance is verified to be greater than 45dB
(LB
longitudinal current limit is determined by increasing the (60Hz)
amplitude of E
is greater than 28mA RMS /Wire. Under this condition, SHD pin
remains high (no false detection) and the 2-wire to 4-wire
longitudinal balance is verified to be greater than 45dB
(LB
metallic balance is computed using the following equation:
BLME = 20 log (E
Figure 4.
metallic to longitudinal balance is defined in this spec.
balance is computed using the following equation:
BLFE = 20 log (E
balance is computed using the following equation:
BMLE = 20 log (E
where: E
balance is computed using the following equation:
BFLE = 20 log (E
where: E
using the following equation:
r = -20 log (2V
the characteristic impedance of the line, nominally 600Ω.
(Reference Figure 6).
is specified at the 4-wire transmit port (V
source (E
(Reference Figure 7). Increase the amplitude of E
THD is measured at V
gain from the 2-wire port to the 4-wire port is equal to 1.
T
are defined in Figure 2.
2-4
2-4
ZT
= 20log VTX/E
= 20log VTX/E
L
TR,
RX,
ZR
G
= V
= 1V
) at the 2-wire port, Z
= V
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
V
V
T
M
L
L
L
L
/A
RMS
R
and E
(Figure 3A) until the 2-wire longitudinal current
(Figure 3B) until the 2-wire longitudinal current
and E
/V
T
L
RX
/A
RX
L
TR
S
/V
/V
R
) where: Z
/V
(0Hz to 100Hz)
/V
TX
until 1% THD is measured at V
TR
L
L
RX
TR
TX
L
).
).
L
), E
), E
), where: E
), E
RX
RX
. Note the PTG pin is open, and the
are defined in Figure 5.
are defined in Figure 5.
RX
L
TR
). R
). R
RX
13
and V
until 1% THD is measured at V
D
= source is removed.
L
L
= 0
= The desired impedance; e.g.,
L
= 600Ω, I
=
= 20kΩ, R
∞
TX
L
TR
TR
, I
ZT
and V
are defined in Figure 4.
) with the signal source at
) with the signal source at
DCMET
, L
TX
ZR
DCMET
TR
) with the signal
, V
L
= 600Ω
= 0mA. Increase
are defined in
T
, V
≥ 18mA.
G
R
TR
until 1%
, A
.
R
and
TR
.
14. Overload Level (4-Wire Port On-Hook) - The overload level
15. Output Offset Voltage - The output offset voltage is specified
16. Two-Wire to Four-Wire Frequency Response - The 2-wire to
18. Four-Wire to Four-Wire Frequency Response - The 4-wire
20. Two-Wire to Four-Wire Insertion Loss (PTG = AGND) - The
21. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire
22. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire
17. Four-Wire to Two-Wire Frequency Response - The 4-wire to 2-
19. Two-Wire to Four-Wire Insertion Loss (PTG = Open) - The
is specified at the 4-wire transmit port (V
source (E
Figure 7). Increase the amplitude of E
measured at V
the 2-wire port to the 4-wire port is equal to 1.
with the following conditions: E
measured at V
4-wire frequency response is measured with respect to
E
The frequency response is computed using the following equation:
F
and compare to 1kHz reading.
V
wire frequency response is measured with respect to E
at 1.0kHz, E
frequency response is computed using the following equation:
F
and compare to 1kHz reading.
V
to 4-wire frequency response is measured with respect to
E
R
following equation:
F
and compare to 1kHz reading.
V
2-wire to 4-wire insertion loss is measured with respect to
E
R
L
where: V
The fuse resistors, R
insertion loss is for R
2-wire to 4-wire insertion loss is measured with respect to E
0dBm at 1.0kHz input signal, E
600Ω and is computed using the following equation:
L
where: V
The fuse resistors, R
insertion loss is for R
insertion loss is measured based upon E
input signal, E
computed using the following equation:
L
where: V
gain tracking is referenced to measurements taken for
E
R
G
-55dBm to -40dBm and compare to -10dBm reading.
V
2-4
2-4
4-2
G
2-4
4-2
4-4
G
TX
TR
RX
L
TX ,
L
G
L
TX
2-4
= 600Ω and is computed using the following equation:
= 600Ω and is computed using the following equation.
= 600Ω. The frequency response is computed using the
= 0dBm at 1.0kHz, E
= 0dBm at 1.0kHz input signal, E
= -10dBm, 1.0kHz signal, E
, V
, R
, R
= 20 log (V
= 20 log (V
= 20 log (V
= 20 log (V
= 20 log (V
= 20 log (V
= 0dBm at 1.0kHz, E
= 20 • log (V
R
TR
L
L
L
and V
and E
TX
TX
TR
and E
G
, R
) at the 2-wire port, Z
, V
, V
, R
G
L
source removed from circuit, R
and E
G
TR
TR
L
TX
TX
RX
TR
RX
TX
TR
TX
TX
TX
TR
and E
source removed from circuit, R
, R
, R
. Note the PTG pin is open, and the gain from
. E
TX
are defined in Figure 8.
are defined in Figure 8.
are defined in Figure 8.
/V
/V
/V
/E
/E
/E
L
L
G
G
/V
RX
RX
TR
F
TR
F
RX
TR
F1
F1
and E
and E
, R
RX
are defined in Figure 8.
, impact the insertion loss. The specified
, impact the insertion loss. The specified
TR
RX
), vary frequency from 300Hz to 3.4kHz
)
)
), vary frequency from 300Hz to 3.4kHz
), vary frequency from 300Hz to 3.4kHz
)
= R
= R
L
) vary amplitude -40dBm to +3dBm, or
, V
are defined in Figure 8.
G
= 0V (VRX input floating), R
G
G
F2
F2
TX
source removed from circuit,
are defined in Figure 8. (Note:
are defined in Figure 8. (Note:
RX
G
= 0).
= 0).
RX
and Z
L
= 0, R
= 0 (VRX input floating), R
= 20kΩ, R
= 0 (VRX output floating),
RX
L
G
L
are defined in Figure 7.
= 0 (VRX input floating),
until 1% THD is
TX
= 600Ω, Z
RX
) with the signal
L
L
= 0dBm, 1.0kHz
= 600Ω. The
L
=
= 600Ω and is
∞
(Reference
L
=
RX
June 1, 2006
L
∞
FN4659.13
= 600Ω.
= 0dBm
and is
G
L
=
=