SC16C750BIA44,518 NXP Semiconductors, SC16C750BIA44,518 Datasheet - Page 15

• Manufacturer Part Number: SC16C750BIA44,518
• Description: IC UART SINGLE W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors
• Type: UART with 64-byte FIFOsr

Specifications of SC16C750BIA44,518

• Number Of Channels: 1, UART
• Package / Case: 44-LCC (J-Lead)
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 3 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2049-2; 935274402518; SC16C750BIA44-T

NXP Semiconductors
7. Register descriptions
Table 8.
[1]
[2]
[3]
SC16C750B_5
Product data sheet
A2 A1 A0 Register Default
General Register Set
0
0
0
0
0
0
1
1
1
1
Special Register Set
0
0
The value shown represents the register’s initialized HEX value; X = n/a.
These registers are accessible only when LCR[7] = 0.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
SC16C750B internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
[3]
[2]
Table 8
assigned bit functions are more fully defined in
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
details the assigned bit functions for the fifteen SC16C750B internal registers. The
[1]
Bit 7
bit 7
bit 7
0
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
0
FIFO
data
error
DCD
bit 7
bit 7
bit 15
Bit 6
bit 6
bit 6
0
RCVR
trigger
(LSB)
FIFOs
enabled
set break set
0
trans.
empty
RI
bit 6
bit 6
bit 14
Rev. 05 — 17 October 2008
Bit 5
bit 5
bit 5
Low
power
mode
64-byte
FIFO
enable
64-byte
FIFO
enable
parity
flow
control
enable
trans.
holding
empty
DSR
bit 5
bit 5
bit 13
Bit 4
bit 4
bit 4
Sleep
mode
reserved
0
even
parity
loopback
break
interrupt
CTS
bit 4
bit 4
bit 12
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Section 7.1
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
OUT2
framing
error
bit 3
bit 3
bit 11
DCD
through
Bit 2
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits word
OUT1
parity
error
bit 2
bit 2
bit 10
RI
SC16C750B
Section
Bit 1
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
© NXP B.V. 2008. All rights reserved.
DSR
7.10.
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
CTS
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