SC16C750BIA44,518 NXP Semiconductors, SC16C750BIA44,518 Datasheet - Page 8

• Manufacturer Part Number: SC16C750BIA44,518
• Description: IC UART SINGLE W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors
• Type: UART with 64-byte FIFOsr

Specifications of SC16C750BIA44,518

• Number Of Channels: 1, UART
• Package / Case: 44-LCC (J-Lead)
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 3 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2049-2; 935274402518; SC16C750BIA44-T

NXP Semiconductors
Table 2.
[1]
6. Functional description
SC16C750B_5
Product data sheet
Symbol
TXRDY
V
GND
IOW
IOW
XTAL1
XTAL2
CC
In Sleep mode, XTAL2 is left floating.
[1]
Pin description
Pin
PLCC44 LQFP64
27
44
22
21
20
18
19
13
40
8
6
4
1
2
The SC16C750B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrity is insured by attaching a parity bit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The SC16C750B is fabricated with an advanced CMOS process to achieve low
drain power and high speed requirements.
The SC16C750B is an upward solution that provides 64 bytes of transmit and receive
FIFO memory, instead of none in the 16C450, or 16 bytes in the 16C550. The
SC16C750B is designed to work with high speed modems and shared network
environments that require fast data processing time. Increased performance is realized in
the SC16C750B by the larger transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable levels of FIFO trigger interrupt and automatic hardware flow control is uniquely
provided for maximum data throughput performance, especially when operating in a
multi-channel environment. The combination of the above greatly reduces the bandwidth
requirement of the external controlling CPU, increases performance, and reduces power
consumption.
The SC16C750B is capable of operation up to 3 Mbit/s with a 48 MHz external clock input
(at 5 V).
…continued
HVQFN32
15
27
13
-
11
9
10
Type
O
Power 2.5 V, 3 V or 5 V supply voltage.
Power Ground voltage.
I
I
I
O
Rev. 05 — 17 October 2008
Description
Transmitter ready. Transmitter DMA signaling is available with
TXRDY. When operating in the FIFO mode, one of two types of
DMA signaling can be selected using FCR[3]. When operating in
the 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports
single-transfer DMA in which a transfer is made between CPU bus
cycles. Mode 1 supports multi-transfer DMA in which multiple
transfers are made continuously until the transmit FIFO has been
filled.
Write inputs. When either IOW or IOW is active (LOW or HIGH,
respectively) and while the UART is selected, the CPU is allowed to
write control words or data into a selected UART register. Only one
of these inputs is required to transfer data during a write operation;
the other input should be tied to its inactive level (that is, IOW tied
LOW or IOW tied HIGH).
Crystal connection or External clock input.
Crystal connection or the inversion of XTAL1 if XTAL1 is
driven.
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
SC16C750B
© NXP B.V. 2008. All rights reserved.
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