TJA1042T NXP Semiconductors, TJA1042T Datasheet - Page 6

• Manufacturer Part Number: TJA1042T
• Manufacturer: NXP Semiconductors

Specifications of TJA1042T

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
TJA1042
Product data sheet
7.2.1 TXD dominant time-out function
7.2.2 Bus dominant time-out function
7.2.3 Internal biasing of TXD and STB input pins
7.2.4 Undervoltage detection on pins V
7.2.5 Overtemperature protection
7.3.1 SPLIT pin
7.2 Fail-safe features
7.3 SPLIT output pin and V
A ‘TXD dominant time-out’ timer is started when pin TXD is set LOW. If the LOW state on
pin TXD persists for longer than t
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD is set to HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 40 kbit/s.
In Standby mode a 'bus dominant time-out' timer is started when the CAN bus changes
from recessive to dominant state. If the dominant state on the bus persists for longer than
t
(due to a bus short-circuit or a failure in one of the other nodes on the network) from
generating a permanent wake-up request. The bus dominant time-out timer is reset when
the CAN bus changes from dominant to recessive state.
Pins TXD and STB have internal pull-ups to
one or both of these pins are left floating. Pull-up currents flow in these pins in all states;
both pins should be held HIGH in Standby mode to minimize standby current.
Should V
will switch to Standby mode. The logic state of pin STB will be ignored until V
recovered.
Should
switch off and disengage from the bus (zero load) until V
The output drivers are protected against overtemperature conditions. If the virtual junction
temperature exceeds the shutdown junction temperature, T
disabled until the virtual junction temperature falls below T
recessive again. Including the TXD condition ensures that output driver oscillation due to
temperature drift is avoided.
Two versions of the TJA1042 are available, only differing in the function of a single pin.
Pin 5 is either a SPLIT output pin or a V
Using the SPLIT pin on the TJA1042T in conjunction with a split termination network (see
Figure 3
will reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with
poor bus leakage performance). In Normal mode, pin SPLIT delivers a DC output voltage
of 0.5V
to(dom)bus
CC
V
IO
and
, the RXD pin is reset to HIGH. This function prevents a clamped dominant bus
CC
. In Standby mode or when V
drop below the
drop below the V
Figure
All information provided in this document is subject to legal disclaimers.
6) can help to stabilize the recessive voltage level on the bus. This
Rev. 6 — 23 March 2011
V
IO
CC
IO
undervoltage detection level, V
undervoltage detection level, V
supply pin
to(dom)TXD
High-speed CAN transceiver with Standby mode
CC
CC
IO
is off, pin SPLIT is floating.
supply pin.
, the transmitter is disabled, releasing the bus
and V
V
IO
to ensure a safe, defined state in case
IO
IO
j(sd)
has recovered.
j(sd)
uvd(VIO)
and TXD becomes
, the output drivers will be
uvd(VCC)
, the transceiver will
, the transceiver
TJA1042
© NXP B.V. 2011. All rights reserved.
CC
has
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