SCC2691AC1A28,602 NXP Semiconductors, SCC2691AC1A28,602 Datasheet - Page 4

• Manufacturer Part Number: SCC2691AC1A28,602
• Description: IC UART SINGLE 28-PLCC
• Manufacturer: NXP Semiconductors

Specifications of SCC2691AC1A28,602

• Features: False-start Bit Detection
• Number Of Channels: 1, UART
• Fifo's: 3Bit
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1212-5; 933811550602; SCC2691AC1A28

Philips Semiconductors
PIN DESCRIPTION
2006 Aug 04
Universal asynchronous receiver/transmitter (UART)
MNEMONIC
MNEMONIC
D0–D7
CEN
WRN
RDN
A0–A2
RESET
INTRN
X1/CLK
X2
RxD
TxD
MPO
MPI
V
GND
CC
22–15
DIP
8–6
14
23
13
10
24
12
11
1
9
2
3
4
5
PIN NO.
27, 25,
PLCC
22–18
11–9
24,
17
28
14
16
12
13
15
2
3
4
5
6
1
TYPE
TYPE
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
NAME AND FUNCTION
NAME AND FUNCTION
Data Bus: Active-high 8-bit bidirectional 3-State data bus. Bit 0 is the LSB and bit 7 is the
MSB. All data, command, and status transfers between the CPU and the UART take place
over this bus. The direction of the transfer is controlled by the WRN and RDN inputs when
the CEN input is low. When the CEN input is high, the data bus is in the 3-State condition.
Chip Enable: Active-low input. When low, data transfers between the CPU and the UART
are enabled on D0–D7 as controlled by the WRN, RDN and A0–A2 inputs. When CEN is
high, the UART is effectively isolated from the data bus and D0–D7 are placed in the 3-State
condition.
Write Strobe: Active-low input. A low on this pin while CEN is low causes the contents of
the data bus to be transferred to the register selected by A0–A2. The transfer occurs on the
trailing (rising) edge of the signal.
Read Strobe: Active-low input. A low on this pin while CEN is low causes the contents of
the register selected by A0–A2 to be placed on the data bus. The read cycle begins on the
leading (falling) edge of RDN.
Address Inputs: Active-high address inputs to select the UART registers for read/write
operations.
Reset: Master reset. A high on this pin clears the status register (SR), the interrupt mask
register (IMR), and the interrupt status register (ISR), sets the mode register pointer to MR1,
and places the receiver and transmitter in the inactive state causing the TxD output to go to
the marking (high) state. Clears Test modes.
Interrupt Request: This active-low output is asserted upon occurrence of one or more of
seven maskable interrupting conditions. The CPU can read the interrupt status register to
determine the interrupting condition(s). This open-drain output requires a pull-up resistor.
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate
frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see
Figure 7, Clock Timing.
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin
not connected although it is permissible to ground it.
Receiver Serial Data Input: The least significant bit is received first. If external receiver
clock is specified, this input is sampled on the rising edge of the clock.
Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the marking (high) condition when the transmitter is idle or disabled and when the
UART is operating in local loopback mode. If external transmitter is specified, the data is
shifted on the falling edge of the transmitter clock.
Multi-Purpose Output: One of the following functions can be selected for this output pin by
programming the auxiliary control register:
RTSN – Request to send active-low output. This output is asserted and negated via the
command register. By appropriate programming of the mode registers, RTSN can be pro-
grammed to be automatically reset after the character in the transmitter is completely shifted
or when the receiver FIFO and shift register are full.
C/TO – The counter/timer output.
TxC1X – The 1X clock for the transmitter.
TxC16X – The 16X clock for the transmitter.
RxC1X – The 1X clock for the receiver.
RxC16X – The 16X clock for the receiver.
TxRDY – The transmitter holding register empty signal. Active-low output. (Open drain)
RxRDY/FFULL – The receiver FIFO not empty/full signal. Active-low output. (Open drain)
Multi-Purpose Input: This pin can serve as an input for one of the following functions:
GPI – General purpose input. The current state of the pin can be determined by reading the
ISR.
CTSN – Clear-to-send active-low input.
CTCLK – Counter/timer external clock input.
RTCLK – Receiver and/or transmitter external clock input. This may be a 1X or 16X clock as
programmed by CSR[3:0] or CSR[7:4].
Pin has an internal V
Power Supply: +5V supply input.
Ground
CC
4
pull-up device supplying 1 to 4 A of current.
SCC2691
Product data sheet