SCC2691AC1A28,602 NXP Semiconductors, SCC2691AC1A28,602 Datasheet - Page 6

• Manufacturer Part Number: SCC2691AC1A28,602
• Description: IC UART SINGLE 28-PLCC
• Manufacturer: NXP Semiconductors

Specifications of SCC2691AC1A28,602

• Features: False-start Bit Detection
• Number Of Channels: 1, UART
• Fifo's: 3Bit
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1212-5; 933811550602; SCC2691AC1A28

1. Parameters are valid over specified temp. range. See Ordering Information table for applicable operating temp. and V
2. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0V and 3.0V with a transition time of
3. Typical values are at +25 C, typical supply voltages, and typical processing parameters.
4. Test condition for outputs: C
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
6. If CEN is used as the ‘strobing’ input, this parameter defines the minimum high time between one CEN and the next. The RDN signal must
7. Consecutive write operations to the command register require at least three rising edges of the X1 clock between writes.
8. These parameters are guaranteed by design, but are not 100% tested in production.
9. Operation to 0MHz is assured by design. Minimum test frequency is 2MHz.
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS
NOTES:
2006 Aug 04
Reset timing (Figure 3)
t
Bus timing (Figure 4)
t
t
t
t
t
t
t
t
t
t
MPI and MPO timing (Figure 5)
t
t
t
Interrupt timing (Figure 6)
t
Clock timing (Figure 7)
t
f
t
f
t
f
t
f
Transmitter timing (Figure 8)
t
t
Receiver timing (Figure 9)
t
t
RES
AS
AH
CS
CH
RW
DD
DF
DS
DH
RWD
PS
PH
PD
IR
CLK
CLK
CTC
CTC
RX
RX
TX
TX
TXD
TCS
RXS
RXH
SYMBOL
SYMBOL
Universal asynchronous receiver/transmitter (UART)
20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and
output voltages of 0.8V and 2V as appropriate.
case, all timing specifications apply referenced to the falling and rising edges of CEN. CEN and RDN (also CEN and WRN) are ORed inter-
nally. As a consequence, this signal asserted last initiates the cycle and the signal negated first terminates the cycle.
be negated for t
8
8
9
8
Reset pulse width
A0–A2 setup time to RDN, WRN low
A0–A2 hold time from RDN, WRN low
CEN setup time to RDN, WRN low
CEN hold time from RDN, WRN high
WRN, RDN pulse width
Data valid after RDN low
Data bus floating after RDN high
Data setup time before WRN high
Data hold time after WRN high
Time between reads and/or writes
MPI input setup time before RDN low
MI input hold time after RDN low
MPO output valid after WRN high
INTRN negated
X1/CLK high or low time
X1/CLK frequency
Counter/timer clock high or low time
Counter/timer clock frequency
RxC high or low time
RxC frequency (16X)
RxC frequency (1X)
TxC high or low time
TxC frequency (16X)
TxC frequency (1X)
TxD output delay from TxC external clock input on IP pin
Output delay from TxC low at OP pin to TxD data output
RxD data setup time before RxC high at external clock input on IP pin
RxD data hold time after RxC high at external clock input on IP pin
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY, TxEMT interrupt)
Reset command (break change interrupt)
Reset command (MPI change interrupt)
Stop C/T command (counter interrupt)
Write IMR (clear of interrupt mask bit)
RWD
5
guarantee that any status register changes are valid.
L
= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C
5
PARAMETER
PARAMETER
6, 7
1, 2, 3, 4
6
Min
100
100
150
150
100
100
220
220
100
100
10
50
30
30
30
0
0
0
0
0
0
0
0
0
LIMITS
3.6864
Typ
L
= 50pF, R
L
= 2.7k
CC
Max
125
370
370
370
370
370
370
270
350
150
110
4.0
4.0
2.0
1.0
2.0
1.0
supply range.
SCC2691
Product data sheet
to V
CC
.
UNIT
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns