82V3002PVG8 IDT, Integrated Device Technology Inc, 82V3002PVG8 Datasheet

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82V3002PVG8

Manufacturer Part Number
82V3002PVG8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 82V3002PVG8

Lead Free Status / Rohs Status
Compliant
FEATURES
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
2003 Integrated Device Technology, Inc.
Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3,
Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces
Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces
Supports ITU-T G.812 Type IV clocks for 1544 kbit/s interface and
2048 kbit/s interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for
E1 interface
Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048 MHz
Accepts reference inputs from two independent sources
Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o and C32o output
clock signals
Provides six types of 8 kHz framing pulses: F0o, F8o, F16o, F32o,
RSP and TSP
MON_out
FLOCK
IN_sel
TRST
Fref0
Fref1
RST
TMS
TDI
TCK
OSCi
Input Monitor
JTAG
Input Switch
Invalid Input
Reference
Reference
Detection
Signal
TDO
OSC
TIE_en
OSCo
WAN PLL WITH DUAL
REFERENCE INPUTS
MODE_sel1
State Control Circuit
TCLR
MODE_sel0
TIE Control
Block
Normal Holdover
VDD
1
VSS
Feedback
Signal
Holdover frequency accuracy of 0.025 ppm
Phase slope of 5 ns/125 s
Attenuates wander from 2.1 Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
MTIE of 600 ns
JTAG boundary scan
Holdover status indication
Freerun status indication
Normal status indication
Lock status indication
Input primary reference quality indication
3.3 V operation with 5 V tolerant I/O
Package available: 56 pin SSOP
Reference
Virtual
VDD
Freerun
VSS
Frequency Select
F_sel1
VDD
Circuit
DPLL
VSS
F_sel0
VDD
VSS
JANUARY 14, 2003
PRELIMINARY
C1.5o
C32o
C3o
F8o
C16o
C8o
C4o
C2o
C6o
F16o
F32o
RSP
F0o
TSP
LOCK
IDT82V3002
DSC-6041/3

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82V3002PVG8 Summary of contents

Page 1

FEATURES Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces Supports ITU-T G.812 Type IV clocks for 1544 kbit/s interface and ...

Page 2

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS DESCRIPTION The IDT82V3002 is a WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to the 2.048 MHz, ...

Page 3

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS PIN DESCRIPTION Name Type Pin Number 12, 18 Power SS 38, 47 13, 19 Power DD 37, 48 OSCo (CMOS OSCi (CMOS Fref0 I 5 ...

Page 4

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS PIN DESCRIPTION (CONTINUED) Name Type Pin Number FREERUN (CMOS MON_out O 7 C32o (CMOS C16o (CMOS C8o (CMOS C4o (CMOS C2o (CMOS) O ...

Page 5

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS FUNCTIONAL DESCRIPTION The IDT82V3002 is a WAN PLL with dual reference inputs, providing timing (clock) and synchronization (framing) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links. See the ...

Page 6

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS Holdover (S2). At the stage of S2 IN_sel transient is detected, the device will change to the Short Time Holdover Mode (S4) with the TIE Control Block disabled. Otherwise, if the ...

Page 7

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS automatically enables the Holdover Mode (Auto-Holdover) when the frequency of the incoming signal is out of the capture range (See AC Electrical Characteristics - Performance). This includes a complete loss of input reference, ...

Page 8

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS Ref1 Ref2 Time = 0.00 s Time = 0.25 s Time = 0.50 s Time = 0.75 s Time = 1.0 s Time = 1.25 s Time = 1.50 s Time = 1.75 ...

Page 9

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS Fraction_T1 Fraction_C6 Loop Filter to the Digital Control Oscillator, at which a E1, T1 and C6 signals are generated. Fraction Block By applying some algorithms on the incoming E1 signal, the Fraction_C6 and ...

Page 10

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS must be no greater than ±32 ppm. Another consideration in determining the accuracy of the master timing source is the desired capture range. The sum of the accuracy of the master timing source ...

Page 11

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS MEASURES OF PERFORMANCE The following are some synchronizer performance indicators and their corresponding definitions. INTRINSIC JITTER Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It ...

Page 12

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS may accumulate up to 200 ns over many frames. The rate of change of the 200 ns phase shift is limited to a maximum phase slope of approximately 5 ns/125 s. This meets ...

Page 13

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS ABSOLUTE MAXIMUM RATINGS Rating Min. Power Supply Voltage -0.5 Voltage on Any Pin with -0.5 Respect to Ground Package Power Dissipation Storage Temperature -55 NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM ...

Page 14

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS AC ELECTRICAL CHARACTERISTICS Performance Description Freerun Mode accuracy with OSCi ppm Freerun Mode accuracy with OSCi ppm Freerun Mode accuracy with OSCi at : 100 ppm Holdover ...

Page 15

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS Intrinsic Jitter Unfiltered Description Intrinsic jitter at F8o ( 8 kHz ) Intrinsic jitter at F0o ( 8 kHz ) Intrinsic jitter at F16o ( 8 kHz ) Intrinsic jitter at C1.5o ( ...

Page 16

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS 2.048 MHz Input to 2.048 MHz Output Jitter Transfer Description Jitter at output for 1 Hz@3.00 UIpp input Jitter at output for 1 Hz@3.00 UIpp input with 100 Hz filter ...

Page 17

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS † Notes: Voltages are with respect to ground (V ) unless otherwise stated. SS Supply voltage and operating temperature are as per Recommended Operating Conditions. Timing parameters are as per AC Electrical Characteristics ...

Page 18

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS TIMING CHARACTERISTICS Timing Parameter Measurement Voltage Levels* Parameter V Threshold Voltage T V Rise and Fall Threshold Voltage High HM V Rise and Fall Threshold Voltage Low LM ALL SIGNALS t t IRF, ...

Page 19

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS Fref0/Fref1 8 kHz Fref0/Fref1 1.544 MHz Fref0/Fref1 2.048 MHz F8o R15D R2D t RW Figure 11. Input to Output Timing (Normal Mode) 19 INDUSTRIAL TEMPERATURE RANGE t ...

Page 20

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS F8o F0o F16o F32o C32o C16o C8o t C4W C4o C2o t C6o C3o C1.5o t F16WL t F16S t C32W t C16WL t t C8W C8W t C4W t C2W t C6W ...

Page 21

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS F8o C2o RSP TSP F8o MODE_sel0 MODE_sel1 TIE_en IN_sel t RSPD t TSPW t TSPD Figure 13. Output Timing Figure 14. Input Control Setup and Hold Timing 21 ...

Page 22

ORDERING INFORMATION XXXXXXX IDT Device Type Data Sheet Document History 06/21/2002 pg. 3 07/22/2002 pgs 08/15/2002 pgs 01/09/2003 pgs CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 *To ...

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