82V3002PVG8 IDT, Integrated Device Technology Inc, 82V3002PVG8 Datasheet - Page 11

• Manufacturer Part Number: 82V3002PVG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3002PVG8

• Lead Free Status / Rohs Status: Compliant

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS
MEASURES OF PERFORMANCE
corresponding definitions.
INTRINSIC JITTER
measured at its output. It is measured by applying a reference signal with
no jitter to the input of the device, and measuring its output jitter. Intrinsic
jitter may also be measured when the device is in a non-synchronizing
mode, such as free running or holdover, by measuring the output jitter of
the device. Intrinsic jitter is usually measured with various band limiting
filters depending on the applicable standards. In the IDT82V3002, the
intrinsic Jitter is limited to less than 0.02 UI on the 2.048 MHz and 1.544
MHz clocks.
JITTER TOLERANCE
(i.e., remain in lock and or regain lock in the presence of large jitter
magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and jitter frequency depends on the
applicable standards.
JITTER TRANSFER
output of a device for a given amount of jitter at the input of the device.
Input jitter is applied at various amplitudes and frequencies, and output jitter
is measured with various filters depending on the applicable standards.
attenuation. This includes the internal 2.1 Hz low pass loop filter and the
phase slope limiter. The phase slope limiter limits the output phase slope
to 5 ns/125 s. Therefore, if the input signal exceeds this rate, such as for
very large amplitude low frequency input jitter, the maximum output phase
slope will be limited (i.e., attenuated) to 5 ns/125 s.
frequencies for a total of 39 possible jitter transfer functions. Since all
outputs are derived from the same signal, the jitter transfer values for the
three cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz and 2.048 MHz to
2.048 MHz can be applied to all outputs.
to 1 UI at 2.048 MHz, which is 488 ns. Consequently, a transfer value
using different input and output frequencies must be calculated in common
units (e.g., seconds).
combinations of inputs and outputs based on the three jitter transfer
functions provided. Note that the resulting jitter transfer functions for all
combinations of inputs (8 kHz, 1.544 MHz, 2.048 MHz) and outputs (8 kHz,
1.544 MHz, 3.088 MHz, 6.312 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz,
16.384 MHz, 32.768 MHz) for a given input signal (jitter frequency and jitter
amplitude) are the same.
lower for small input jitter signals than for large ones. Consequently,
accurate jitter transfer function measurements are usually made with large
input jitter signals (e.g., 75% of the specified maximum jitter tolerance).
FREQUENCY ACCURACY
The following are some synchronizer performance indicators and their
Intrinsic jitter is the jitter produced by the synchronizing circuit and is
Jitter tolerance is a measure of the ability of a DPLL to operate properly
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the
For the IDT82V3002, two internal elements determine the jitter
The IDT82V3002 has fourteen outputs with three possible input
It should be noted that 1 UI at 1.544 MHz is 644 ns, which is not equal
Using the above method, the jitter attenuation can be calculated for all
Since intrinsic jitter is always present, jitter attenuation will appear to be
Frequency accuracy is defined as the absolute tolerance of an output
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clock signal when it is not locked to an external reference, but is operating
in a free running mode. For the IDT82V3002, the Freerun accuracy is
equal to the Master Clock (OSCi) accuracy.
HOLDOVER ACCURACY
clock signal, when it is not locked to an external reference signal, but is
operating using storage techniques. For the IDT82V3002, the storage
value is determined while the device is in Normal Mode and locked to an
external reference signal.
not affect Holdover accuracy, but the change in OSCi accuracy while in
Holdover Mode does.
CAPTURE RANGE
which the synchronizer must be able to pull into synchronization. The
IDT82V3002 capture range is equal to ±230 ppm minus the accuracy of
the master clock (OSCi). For example, a 32 ppm master clock results in a
capture range of 198 ppm.
should be able to reject references that are off the nominal frequency by
more than ±12 ppm. The IDT82V3002 provides one pin, MON_out, to
indicate whether the primary reference are within the ±12 ppm of the
nominal frequency.
LOCK RANGE
able to maintain synchronization. The lock range is equal to the capture
range for the IDT82V3002.
PHASE SLOPE
a given signal changes phase with respect to an ideal signal. The given
signal is typically the output signal. The ideal signal is of constant frequency
and is nominally equal to the value of the final output signal or final input
signal.
TIME INTERVAL ERROR (TIE)
signal.
MAXIMUM TIME INTERVAL ERROR (MTIE)
and an ideal timing signal within a particular observation period.
PHASE CONTINUITY
and an ideal timing signal at the end of a particular observation period.
Usually, the given timing signal and the ideal timing signal are of the same
frequency. Phase continuity applies to the output of the synchronizer after
a signal disturbance due to a mode change. The observation period is
usually the time from the disturbance, to just after the synchronizer has
settled to a steady state.
maintained to within ±5 ns at the instance (over one frame) of all mode
changes. The total phase shift, depending on the type of mode change,
Holdover accuracy is defined as the absolute tolerance of an output
The absolute Master Clock (OSCi) accuracy of the IDT82V3002 does
Also referred to as pull-in range. This is the input frequency range over
The Telcordia GR-1244-CORE standard, recommends that the DPLL
This is the input frequency range over which the synchronizer must be
Phase slope is measured in seconds per second and is the rate at which
TIE is the time delay between a given timing signal and an ideal timing
MTIE is the maximum peak to peak delay between a given timing signal
Phase continuity is the phase difference between a given timing signal
In the case of the IDT82V3002, the output signal phase continuity is
INDUSTRIAL TEMPERATURE RANGE