82V3002PVG8 IDT, Integrated Device Technology Inc, 82V3002PVG8 Datasheet - Page 12

• Manufacturer Part Number: 82V3002PVG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3002PVG8

• Lead Free Status / Rohs Status: Compliant

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS
may accumulate up to 200 ns over many frames. The rate of change of the
200 ns phase shift is limited to a maximum phase slope of approximately
5 ns/125 s. This meets the AT&T TR62411 maximum phase slope
requirement of 7.6 ns/125 s and Telcordia GR-1244-CORE (81 ns/1.326
ms).
PHASE LOCK TIME
Phase lock occurs when the input signal and output signal are not
changing in phase with respect to each other (not including jitter).
factors, which include:
achieve due to other synchronizer requirements. For instance, better jitter
transfer performance is achieved with a lower frequency loop filter which
increases lock time. And better (smaller) phase slope performance (limiter)
results in longer lock times. The IDT82V3002 loop filter and limiter were
optimized to meet the AT&T TR62411 jitter transfer and phase slope
requirements. Consequently, phase lock time, which is not a standards
requirement, may be longer than in other applications. See AC Electrical
Characteristics - Performance for Maximum Phase Lock Time.
enables the DPLL to lock to an incoming reference within approximately
500 ms.
This is the time it takes the synchronizer to phase lock to the input signal.
Lock time is very difficult to determine because it is affected by many
Although a short lock time is desirable, it is not always possible to
IDT82V3002 provides a fast lock pin (FLOCK), which, when set high
i) Initial input to output phase difference
ii) Initial input to output frequency difference
iii) Synchronizer loop filter
iv) Synchronizer limiter
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INDUSTRIAL TEMPERATURE RANGE