82V3002PVG8 IDT, Integrated Device Technology Inc, 82V3002PVG8 Datasheet - Page 3

• Manufacturer Part Number: 82V3002PVG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3002PVG8

• Lead Free Status / Rohs Status: Compliant

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS
PIN DESCRIPTION
MODE_sel1
MODE_sel0
HOLDOVER
NORMAL
F_sel1
F_sel0
FLOCK
TIE_en
IN_sel
LOCK
Name
OSCo
Fref0
Fref1
TCLR
OSCi
RST
V
V
SS
DD
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) I
Power
Power
Type
I
I
I
I
I
I
I
I
I
I
I
Pin Number
12, 18, 27
13, 19, 26
38, 47
37, 48
49
50
11
10
56
45
44
52
46
5
6
9
2
1
4
3
Ground.
0 V. All V
Positive Supply Voltage.
All V
Oscillator Master Clock.
For crystal operation, a 20 MHz crystal is connected from this pin to OSCi. For clock oscillator operation, this
pin is left unconnected.
Oscillator Master Clock.
For crystal operation, a 20 MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this
pin is connected to a clock source.
Reference Input 0.
This is one of the input reference sources (falling edge) used for synchronization. One of three possible
frequencies (8 kHz, 1.544 MHz, or 2.048 MHz) may be used. The selection of the input reference is based
upon IN_sel control input. See Table 3. The Fref0 pin is internally pulled up to V
Reference Input 1.
See Pin description for Fref0. This pin is internally pulled up to V
Reference Switch Input Control.
A logic low selects Reference Input 0 (Fref0) and a logic high selects Reference Input 1 (Fref1). The logic
level of this input is gated in by the rising edge of F8o. This Pin is internally pulled down to V
Input Frequency Select 1 .
This input, in conjunction with F_sel0, selects which of three possible frequencies (8 kHz, 1.544 MHz, or
2.048 MHz ) may be input to the Reference Input 0 and Reference Input 1. See Table 2.
Input Frequency Select 0.
See Pin description for F_sel1.
Mode/Control Select 1.
This input, in conjunction with MODE_sel0, determines the state (Normal, Holdover or Freerun) of operation.
The logic level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to V
Table 1.
Mode/Control Select 0.
See pin description for MODE_sel1.The logic level at this input is gated in by the rising edge of F8o This pin
is internally pulled down to V
Reset Input.
A logic low at this pin resets the IDT82V3002. To ensure proper operation, the device must be reset after
reference signal frequency changes and power-up. The RST pin should be held low for a minimum of 300 ns.
While the RST pin is low, all framing and clock outputs are at logic high.
TIE Circuit Reset.
Logic low at this input resets the TIE (Maximum Time Interval Error) control block resulting in a realignment of
output phase with input phase. The TCLR pin should be held low for a minimum of 300 ns. This pin is
internally pulled up to V
TIE Enable.
A logic high at this pin enables the TIE control block while a logic low at this pin disables the TIE control
block. The logic level at this input is gated in by the rising edging of F8o. This pin is internally pulled up to
V
Fast Lock Mode.
Set high to allow the DPLL to quickly lock to the input reference (less than 500 ms locking time).
Lock Indicator.
This output goes high when the DPLL is frequency locked to the input reference.
Holdover Indicator.
This output goes to a logic high whenever the DPLL goes into Holdover Mode.
Normal Indicator.
This output goes to a logic high whenever the DPLL goes into Normal Mode.
DD
.
DD
pins should be connected to +3.3 V nominal.
SS
pins should be connected to the ground.
DD
.
3
SS
.
Description
INDUSTRIAL TEMPERATURE RANGE
DD
.
DD
.
SS
.
SS
. See