82V3002PVG8 IDT, Integrated Device Technology Inc, 82V3002PVG8 Datasheet - Page 6

• Manufacturer Part Number: 82V3002PVG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3002PVG8

• Lead Free Status / Rohs Status: Compliant

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS
Holdover (S2). At the stage of S2, if an IN_sel transient is detected, the
device will change to the Short Time Holdover Mode (S4) with the TIE
Control Block disabled. Otherwise, if the input reference becomes valid, the
device will be changed back to Normal (S1) automatically. Refer to “Invalid
Input Reference Detection” for more information.
is determined by the IN_sel pin, which controls the input reference
selection. A transient voltage occurs at the In_sel pin will make the device
change from Normal (S1) to Short Time Holdover (S4) automatically. See
“Reference Input Switch” for details.
control block will be enabled or disabled automatically as shown along the
lines in Figure 2, except the changes from Holdover (S3) to Normal (S1)
and from Short Time Holdover (S4) to Normal (S1), which depend on the
logic level of the TIE_en pin.
Normal Mode
nized to the network is required.
C8o, C16o and C32o) and synchronization (F0o, F8o, F16o, F32o, TSP,
RSP) signals, which are synchronous to one input reference. The input
reference signal have a nominal frequency of 8 kHz, 2.048 MHz or 1.544
MHz.
to make the output signals synchronous (phase locked) to the input refer-
ence.
by setting the NORMAL pin high.
Fast Lock Mode
IDT82V3002 to lock to a reference more quickly than in Normal Mode.
Typically, the DPLL will lock to the input reference within 500 ms if the
FLOCK pin is high.
Holdover Mode
network synchronization is temporarily disrupted.
signals, which are not locked to an external reference signal, but are based
on storage techniques. The storage value is determined while the device
is in Normal Mode and locked to an external reference signal.
reference signal, a numerical value corresponding to the output frequency
is stored alternately in two memory locations every 30 ms. When the
device is switched into Holdover Mode, the stored value from between 30
ms and 60 ms is used to set the output frequency of the device.
corresponds to a worst case of 18 frame (125 s per frame) slips in 24
hours. This meets the AT&T TR62411 and Telcordia GR-1244-CORE
Stratum 3 requirement of ±0.37 ppm (255 frame slips per 24 hours).
into the Holdover Mode.
Freerun Mode
or used when a system is just powered up and the network synchronization
While the changes between Normal (S1) and Short Time Holdover (S4)
When the operating mode is changed from one state to another, the TIE
The Normal Mode is typically used when a slave clock source synchro-
In this mode, the IDT82V3002 provides timing (C1.5o, C3o, C2o, C4o,
From a reset condition, the IDT82V3002 will take maximum 30 seconds
Whenever the IDT82V3002 enters Normal Mode, it will give an indication
Fast Lock Mode is a submode of Normal Mode, it is used for the
Holdover Mode is typically used for short duration (e.g., 2 seconds) while
In Holdover Mode, the IDT82V3002 provides timing and synchronization
In Normal Mode, when the output frequency is locked to the input
The frequency accuracy of Holdover Mode is ±0.025 ppm, which
The HOLDOVER pin is set to logic high whenever the IDT82V3002 goes
Freerun Mode is typically used when a master clock source is required,
6
has not been achieved.
signals which are based on the master clock frequency (OSCi) only, and
are not synchronized to the input reference signal.
clock (OSCi). So if a ±32 ppm output clock is required, the master clock
must also be ±32 ppm. Refer to the “OSC” section for more information.
Freerun Mode.
FREQUENCY SELECT CIRCUIT
MHz. As shown in Table 2, the F_sel1 and F_sel0 pins determine which of
the three frequencies is selected for the reference. Note that both the
reference inputs Fref0 and Fref1 must have the same frequency applied to
them. Every time the frequency selection is changed, the device must be
reset to make the change effective.
TABLE 2
REFERENCE INPUT SWITCH
Fref0 and Fref1, and operates on the falling edges. The reference is
selected by the IN_sel pin, as shown in Table 3. The selected reference
signal is sent to the TIE control block, Reference Input Monitor and Invalid
Input Signal Detection block to be further processed.
TABLE 3
automatically switch to the Short Time Holdover Mode (S4) with the TIE
Control Block disabled. At the S4 stage, if no IN_sel transient occurs, the
reference signal will be changed from one to the other and the device will
switch back to the Normal Mode (S1) automatically. During the change
from S4 to S1, the TIE Control Block can be manually enabled or disabled.
See Figure 2 for full details.
REFERENCE INPUT MONITOR
should be able to reject the references that are off the nominal frequency
by more than ±12 ppm. The IDT82V3002 monitors TIE Control Block input
frequency and outputs a MON_out signal to indicate the monitoring result.
Whenever the reference frequency is off the nominal frequency by more
than ±12 ppm, the MON_out pin goes high. The MON_out signal is
updated every 2 second.
INVALID INPUT SIGNAL DETECTION
In Freerun Mode, the IDT82V3002 provides timing and synchronization
The accuracy of the output clock is equal to the accuracy of the master
The FREERUN pin goes high whenever the IDT82V3002 works in
The frequency of the input reference can be 8 kHz, 1.544 MHz or 2.048
The IDT82V3002 accepts two simultaneous reference input signals
When a transient voltage occurs at the IN_sel pin, the IDT82V3002 will
The Telcordia GR-1244-CORE standard recommends that the DPLL
This circuit monitors the input reference signal to the IDT82V3002 and
F_sel1
0
0
1
1
REFERENCE INPUT SWITCH CONTROL
INPUT REFERENCE SELECTION
IN_sel
0
1
INDUSTRIAL TEMPERATURE RANGE
F_sel0
0
1
0
1
Input Reference
Fref0
Fref1
Input Frequency
1.544 MHz
2.048 MHz
Reserved
8 kHz