SC16C2550BIBS,128 NXP Semiconductors, SC16C2550BIBS,128 Datasheet - Page 20

• Manufacturer Part Number: SC16C2550BIBS,128
• Description: IC DUART SOT617-1
• Manufacturer: NXP Semiconductors

Specifications of SC16C2550BIBS,128

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 3.5 V ~ 4.5 V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280309128; SC16C2550BIBS-F; SC16C2550BIBS-F

NXP Semiconductors
SC16C2550B_5
Product data sheet
7.5 Line Control Register (LCR)
Table 13.
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits and the parity are selected by writing the
appropriate bits in this register.
Table 14.
Table 15.
Bit
7:6
5:4
3:1
0
Bit
7
6
5:3
2
1:0
LCR[5]
X
X
0
0
1
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[0]
Symbol
LCR[7]
LCR[6]
LCR[5:3]
LCR[2]
LCR[1:0]
Interrupt Status Register bits description
Line Control Register bits description
LCR[5:3] parity selection
LCR[4]
X
0
1
0
1
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 05 — 12 January 2009
Description
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
Set break. When enabled, the Break control bit causes a break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
Programs the parity conditions (see
Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not
being used in the 16C450 mode. They are set to a logic 1 when the
FIFOs are enabled in the SC16C2550B mode.
not used
INT priority bits 2:0. These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2 and 3 (see
INT status.
LCR[3]
0
1
1
1
1
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
Table
Table
17).
Table
16).
Table
15)
SC16C2550B
12).
© NXP B.V. 2009. All rights reserved.
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