LXT975BHC Intel Corporation, LXT975BHC Datasheet
LXT975BHC
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LXT975BHC Summary of contents
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... Configurable LED drivers and serial LED output. Configurable through MII serial port or via external control pins. Available in 160-pin PQFP with heat spreader. o Commercial temperature range (0-70 C ambient). Part numbers: — LXT974AHC — LXT974BHC — LXT975AHC — LXT975BHC Order Number: 249274-001 January 2001 ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ...
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Contents 1.0 Pin Assignments and Signal Descriptions 2.0 Functional Description 2.1 Introduction..........................................................................................................19 2.2 Network Media / Protocol Support.......................................................................20 2.2.1 10/100 Mbps Network Interface .............................................................20 2.2.1.1 Twisted-Pair Interface ...............................................................20 2.2.1.2 Fiber Interface ...........................................................................21 2.2.2 MII Interface ...........................................................................................21 2.2.2.1 MII Data Interface......................................................................21 ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 2.7.2 Per Port LEDs ........................................................................................ 38 2.7.2.1 LEDn_0 ..................................................................................... 38 2.7.2.2 LEDn_1 ..................................................................................... 38 2.7.2.3 LEDn_2 ..................................................................................... 38 2.8 Operating Requirements ..................................................................................... 39 2.8.1 Power Requirements.............................................................................. 39 2.8.1.1 MII Power Requirements........................................................... 39 2.8.1.2 ...
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Figures 1 LXT974/975 Block Diagram .................................................................................. 9 2 LXT974 Pin Assignments ...................................................................................10 3 LXT975 Pin Assignments ...................................................................................12 4 LXT974 Switch Application .................................................................................19 5 LXT975 Switch Application .................................................................................20 6 MII Data Interface ...............................................................................................22 7 Loopback Paths ..................................................................................................24 8 Management Interface - ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Tables 1 LXT974 Signal Detect/TP Select Signal Descriptions ......................................... 11 2 LXT974 Twisted-Pair Interface Signal Descriptions............................................ 11 3 LXT974 Fiber Interface Signal Descriptions........................................................ 11 4 LXT975 Signal Detect/TP Select Signal Descriptions ......................................... 13 ...
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Auto Negotiation Link Partner Ability Register (Address 5).................................67 50 Auto Negotiation Expansion (Address 6) ............................................................68 51 LED Configuration Register (Address 16, Hex 10)..............................................68 52 Interrupt Enable Register (Address 17, Hex 11) .................................................69 53 Interrupt Status Register (Address 18, Hex ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Revision History Revision Date 1.4 11/00 8 Description Replace all references to LXT974A and LXT975A with LXT974 and LXT975 (applied to all versions, including A and B) Datasheet ...
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Figure 1. LXT974/975 Block Diagram VCCMII MII_MD<1:0> CFG<2:0> ADDR<4:2> MDIO MDC MDINT TX_ENn MII TX_ERn TXDn<3:0> TRSTEn TX_CLKn RX_CLKn RXDn<3:0> MII CRSn COLn RX_DVn RX_ERn Datasheet Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975 Global Functions MII Power Supply Management / ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT974 Pin Assignments LED3_0 ..... 1 LED3_1 ..... 2 LED3_2 ..... 3 LED2_0 ..... 4 LED2_1 ..... 5 LED2_2 ..... 6 GND ..... 7 LED1_0 ...
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Table 1. LXT974 Signal Detect/TP Select Signal Descriptions 2 1 Pin# Symbol Type Signal Detect - Ports When SD/TPn pins are tied High PECL input, bit 19 and the operating mode ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 3. LXT975 Pin Assignments LED3_0 ..... 1 LED3_1 ..... 2 LED3_2 ..... 3 LED2_0 ..... 4 LED2_1 ..... 5 LED2_2 ..... 6 GND ..... 7 LED1_0 ..... 8 LED1_1 ..... 9 LED1_2 ...
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Table 4. LXT975 Signal Detect/TP Select Signal Descriptions 2 1 Pin# Symbol Type Signal Detect - Ports 1 & 3. When SD/TPn pins are tied High PECL input, bit 19 and the operating mode ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Table 7. LXT974 and LXT975 MII Signal Descriptions 3 1 Pin# Symbol Type 33 TXD0_0 34 TXD0_1 I Transmit Data - Port 0. Inputs containing NRZ data to be transmitted from port 0. ...
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Table 7. LXT974 and LXT975 MII Signal Descriptions (Continued Pin# Symbol Type 27 RX_DV0 46 RX_DV1 Receive Data Valid - Ports These signals are synchronous to the respective O 65 RX_DV2 RX_CLKn. Active High indication ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Table 8. LXT974 and LXT975 Hardware Control Interface Signal Descriptions 1 Pin# Symbol Type Configuration Control 0. When A/N is enabled, Low to High transition on CFG_0 causes auto-negotiate to restart on all ...
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Table 9. LXT974 and LXT975 Miscellaneous Signal Descriptions Pin# Symbol Type 20 ADD4 I 19 ADD3 I 18 ADD2 I 101, 112, 159 TEST I 140 RBIAS I 118 CLK25M I 109 RESET I 102 PWRDN I 41, 119, 120 ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Table 11. LXT974 Power Supply Signal Descriptions Pin# 22, 60, 96 VCC 40, 78 VCCMII 7, 14, 39, 56, 59, 77, 95, 160 GND 21 GNDA 108 GNDH 107 VCCH 128, 137, 147, ...
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Functional Description 2.1 Introduction The LXT974 and LXT975 are four-port Fast Ethernet 10/100 Transceivers that support 10 Mbps and 100 Mbps networks. They comply with all applicable requirements of IEEE 802.3. Each port can directly drive either a 100BASE-TX ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 5. LXT975 Switch Application Fiber Module Fiber LXT974 Module 10/100 Fiber Quad Transceiver Module Fiber Module LXT975 10/100 Quad Transceiver QUAD Transformer 2.2 Network Media / Protocol Support The LXT974/975 supports both ...
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Only a transformer (1:1 on receive side, 2:1 on transmit side), load resistors, and bypass capacitors are needed to complete this interface. Using Intel’s patented waveshaping technology, the transmitter pre-distorts the outgoing signal to reduce the need for external filters ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 6. MII Data Interface LXT974/975 Transmit Clock The LXT974/975 is the master clock source for data transmission. The LXT974/975 automatically sets the speed of TX_CLK to match port conditions. If the port ...
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Carrier Sense Carrier sense (CRS asynchronous output always generated when a packet is received from the line and in some modes when a packet is transmitted. On transmit, CRS is asserted Mbps or ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 7. Loopback Paths 10T Loopback MII Collision The LXT974/975 asserts its collision signal, asynchronously to any clock, whenever the line state is half-duplex and the transmitter and receiver are active at the ...
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Figure 8. Management Interface - Read Frame Structure MDC MDIO 32 "1" (Read) Idle Preamble SFD Op Code Figure 9. Management Interface - Write Frame Structure MDC MDIO 32 "1" (Write) Idle ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Individual chip addressing allows multiple LXT974/975 devices to share the MII in either mode. Table 15 through Table 17 Hardware Control Interface. Table 15. Configuring the LXT974/975 via Hardware Control Desired Configuration 1, ...
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Table 17. Configuring the LXT974/975 with Auto-Negotiation Disabled 1,2 Desired Configuration Per Port (Fiber) Configuration Fiber operation can be forced per port via SD/TPn pins when auto-negotiation is enabled. Per-port settings override the global pin settings. 100FX Full-Duplex Operation. 100FX ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 2.3.3 Link Configuration When the LXT974/975 is first powered on, reset, or encounters a link failure state, it must determine the line speed and operating conditions to use for the network link. The ...
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Auto-Negotiation The LXT974/975 attempts to auto-negotiate with its counterpart across the link by sending Fast Link Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 s apart. Odd link pulses (clock pulses) are always present. Even ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 12. LXT974/975 Auto-Negotiation Operation Disable Auto-Negotiation Go To Forced Settings Done 2.5 100 Mbps Operation 2.5.1 100BASE-X MII Operations The LXT974/975 encodes and scrambles the data sent by the MAC, and then ...
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In 100FX mode, the LXT974/975 transmits and receives NRZI signals across the PECL interface. An external 100FX transceiver module is required to complete the fiber connection. As shown in Figure LXT974/975 detects the start of preamble, it transmits a J/K ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Table 19. 4B/5B Coding 4B Code Code Type ...
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Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT974/975 is a Physical Layer 1 (PHY) device. The LXT974/975 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 2.5.4.2 Data Errors Figure 16 shows normal reception. When the LXT974/975 receives invalid symbols from the line, it asserts RX_ER, as shown in 2.5.4.3 Collision Indication Figure 18 shows normal transmission. The LXT974/975 ...
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PMA Sublayer 2.5.5.1 Link The LXT974/975 supports a Standard link algorithm or Enhanced link algorithm, which can be set via bit 16.1. Link is established when the symbol error rate is less than 64 errors out of 1024 symbols ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 2.5.6.2 Baseline Wander Correction The LXT974/975 provides a baseline wander correction function which makes the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE- definition “unbalanced”. ...
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The LXT974/975 does not support fiber connections at 10 Mbps. 2.6.2.1 Preamble Handling In 10BASE-T Mode, the LXT974/975 strips the entire preamble off of received packets. CRS is asserted a few bit times after carrier is detected. RX_DV is held ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 2.7.1 Serial LED Output The LXT974/975 provides a serial LED interface which should be attached to an external shift register. This interface provides 24 status bits ( ports). Each port reports ...
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Table 20. LED-DAT Serial Port Bit Assignments Port Bit 23 is shifted out first. 2.8 Operating Requirements 2.8.1 Power Requirements The LXT974/975 requires four +5V ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 3.0 Application Information 3.1 Design Recommendations The LXT974/975 is designed to comply with IEEE requirements and to provide outstanding receive Bit Error Rate (BER) and long-line-length performance. Lab testing has shown that the ...
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LXT974/975, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI problems. The recommended implementation is to divide the VCC plane into two ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 3.1.5 The RBIAS Pin The LXT974/975 requires ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from the pin to the resistor, ...
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Magnetics Information The LXT974/975 requires a 1:1 ratio for the receive transformers and a 2:1 ratio for the transmit transformers as shown in protect the circuitry from static voltages across the connectors and cables. Refer to the Magnetic Manufacturers ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 3.3 Twisted-Pair/ RJ-45 Interface Figure 20 shows layout of the LXT974 twisted-pair interface in a single-high RJ-45 modular application. Figure 21 RJ-45 application. Figure 20. Typical LXT974 Twisted-Pair Single RJ-45 Modular Application Port ...
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Figure 21. Typical LXT975 Twisted-Pair Stacked RJ-45 Modular Application Port RJ-45 Footprint Port 2 8 Stacked RJ-45s 1 Port ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 22. LXT974/975 Power and Ground Connections LXT974/975 VCCH GNDH VCCT GNDT RBIAS GNDA VCCR GNDR VCC GND VCCMII 46 .01 F .01 F 22k 1% .01 F Analog Supply Plane Digital Supply ...
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Figure 23. Typical Twisted-Pair Interface and Supply Filtering Output Stage with Compensating Inductor 0.1 F GNDR TPIP TPIN TPOP LXT974/975 TPON VCCT 0.1 F GNDT Datasheet Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975 2:1 200 ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 24. Typical Fiber Interface 0.01 F FIBONn FIBOPn 0.01 F LXT974/975 80 SD/TPn 130 GNDA FIBINn FIBIPn 48 VCCT + GNDA +5 V 191 191 VCCR +5 V 0.1 ...
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Figure 25. Typical MII Interface TX_ENn TXDn<3:0> TX_ERn TX_CLKn MII COLn Data RX_DVn I/F RX_ERn RX_CLKn RXDn<3:0> CRSn TRSTEn MDIO MII Control MDINT I/F MDC MDDIS CFG0 CFG1 H/W CFG2 Control BYPSCR I/F FDE FDE_FX +5 V AUTOENA W 330 ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers 4.0 Test Specifications Note: The minimum and maximum values in represent the performance specifications of the LXT974/975 and are guaranteed by test, except where noted by design. Minimum and maximum values in the ...
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Table 25. Digital I/O Characteristics - MII Pins) Parameter Symbol Input Low voltage Input High voltage Input current Output Low voltage Output High voltage Driver output resistance (Line driver output enabled) 1. Parameter is guaranteed by design; not subject to ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Table 29. 100BASE-FX Transceiver Characteristics Parameter Peak differential output voltage (single ended) Signal rise/fall time Jitter (measured differentially) Peak differential input voltage Common mode input range 1. Typical values are at 25 °C ...
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Figure 26. MII - 100BASE-TX Receive Timing TPIP CRS TRSTE RX_DV RXD<3:0> RX_CLK COL Table 31. MII - 100BASE-TX Receive Timing Parameters Parameter RXD, RX_DV, RX_ER setup to RX_CLK High RXD, RX_DV, RX_ER hold from RX_CLK High CRS asserted to ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 27. MII - 100BASE-TX Transmit Timing TXCLK TX_EN TXD<3:0> TPOP CRS Table 32. MII - 100BASE-TX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from ...
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Figure 28. MII - 100BASE-FX Receive Timing 0ns FIBIP CRS 1 TRSTE RX_DV RXD<3:0> RX_CLK COL Table 33. MII - 100BASE-FX Receive Timing Parameters Parameter RXD, RX_DV, RX_ER setup to RX_CLK High RXD, RX_DV, RX_ER hold from RX_CLK High CRS ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 29. MII - 100BASE-FX Transmit Timing TXCLK TX_EN TXD<3:0> FIBOP CRS Table 34. MII - 100BASE-FX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from ...
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Figure 30. MII - 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS t 6 TPI t 8 COL Table 35. MII - 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER setup to RX_CLK High RXD, RX_DV, RX_ER hold from RX_CLK ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 31. MII - 10BASE-T Transmit Timing TX_CLK t 1 TXD, TX_EN, TX_ER t 3 CRS TPO Table 36. MII - 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High ...
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Figure 33. 10BASE-T Jab and Unjab Timing TX_EN TXD COL Table 38. 10BASE-T Jab and Unjab Timing Parameters Parameter Maximum transmit time Unjab time 1. Typical values are at 25 °C and are for design aid only; not guaranteed and ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 34. Auto Negotiation and Fast Link Pulse Timing Clock Pulse TPOP t1 Figure 35. Fast Link Pulse Timing FLP Burst TPOP t4 Table 39. Auto Negotiation and Fast Link Pulse Timing Parameters ...
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Figure 36. MDIO Timing when Sourced by STA MDC MDIO Figure 37. MDIO Timing When Sourced by PHY MDC MDIO Table 40. MII Timing Parameters Parameter Sym MDIO setup before MDC MDIO hold after MDC MDC to MDIO output delay ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Figure 38. Power Down Timing VCC RESET MDIO,etc Table 41. Power Down Timing Parameters Parameter Power Down recovery time 1. Typical values are at 25° C and are for design aid only; not ...
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Register Definitions The LXT974/975 register set includes a total of 48 16-bit registers, 12 registers per port. Refer to Table 43 for a complete register listing. • Seven base registers (0 through 6) are defined in accordance with the ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Table 44. Control Register Bit Name 1 = Reset port. 0.15 Reset 0 = Enable normal operation Enable loopback mode. 0.14 Loopback 0 = Disable loopback mode. Speed 1 = 100 ...
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Table 45. Status Register (Address 1) Bit Name 1.15 100BASE-T4 Not supported. 100BASE-X 1. Port able to perform full-duplex 100BASE-X. Full-Duplex 100BASE-X 1. Port able to perform half-duplex 100BASE-X. Half-Duplex 10 Mbps 1. Port ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Table 46. PHY Identification Register 1 (Address 2) Bit Name PHY ID 2.15:0 The PHY identifier composed of bits 3 through 18 of the OUI. Number Read Only Table 47. ...
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Table 48. Auto Negotiation Advertisement Register (Address 4) Bit Name 4.15 Next Page Not supported. 4.14 Reserved Ignore Remote fault. 4.13 Remote Fault remote fault. 4.12:11 Reserved Ignore Pause operation is enabled for ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Table 49. Auto Negotiation Link Partner Ability Register (Address 5) (Continued) Bit Name 1 = Pause operation is enabled for link partner. 5.10 Pause 0 = Pause operation is disabled Link ...
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Table 51. LED Configuration Register (Address 16, Hex 10) Bit Name Determine condition indicated by LED_2 bit 7 0 16.7:6 LED_2 Select Determine condition indicated by LED_1 bit 5 0 16.5:4 LED_1 Select Determine ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Table 53. Interrupt Status Register (Address 18, Hex 12) Bit Name 1 = Indicates MII interrupt pending. 18.15 MINT 0 = Indicates no MII interrupt pending. This bit is cleared by reading Register ...
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Table 54. Port Configuration Register (Address 19, Hex 13) (Continued) Bit Name Scrambler 1 = Bypass transmit scrambler and receive descrambler. Bypass 19 Normal operation (scrambler and descrambler enabled). (100BASE-T only Enable 100BASE fiber interface. 19.2 ...
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers Table 55. Port Status Register (Address 20, Hex 14) (Continued) Bit Name 1 = MLT3 encoding error detected. MLT3 20.4 Encoding Error MLT3 encoding error detected. 20.3 Reserved Ignore. Low-Voltage ...
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... Figure 41. LXT974/975 Package Specification 160-Pin PQFP with Heat Spreader o • (Commercial Temp • Part Number LXT974AHC • Part Number LXT975AHC • Part Number LXT974BHC • Part Number LXT975BHC Table 56. QUAD FLAT PACKAGE All Dimensions in millimeters Dim. Min. Typ. A --- 3.70 A 0.25 0. ...
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