CS82C37A-12 Intersil Corporation, CS82C37A-12 Datasheet
CS82C37A-12
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CS82C37A-12 Summary of contents
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... Each channel has a full 64K address and word count range, and may be programmed to autoinitialize these registers following DMA termination (end of process). 12.5MHz PACKAGE CP82C37A- PDIP IP82C37A-12 CS82C37A- PLCC IS82C37A-12 CD82C37A- CERDIP ID82C37A-12 MD82C37A-12/B 5962-9054303MQA SMD# ...
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Pinouts 82C37A (PDIP/CERDIP) TOP VIEW IOR 1 IOW 2 MEMR 3 MEMW READY 6 HLDA 7 ADSTB 8 AEN 9 HRQ CLK 12 RESET 13 DACK2 14 DACK3 15 DREQ3 16 DREQ2 17 DREQ1 ...
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Pin Description PIN SYMBOL NUMBER TYPE decoupling. GND 20 Ground CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A operations. This input may be driven from ...
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Pin Description (Continued) PIN SYMBOL NUMBER TYPE EOP 36 I/O END OF PROCESS: End of Process (EOP active low bidirectional signal. Information concerning the completion of DMA services is available at the bidirectional EOP pin. The 82C37A allows ...
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Functional Description The 82C37A direct memory access controller is designed to improve the data transfer rate in systems which must transfer data from an I/O device to memory, or move a block of memory to an I/O device. It will ...
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The 82C37A can assume seven separate states, each composed of one full clock period. State I (SI) is the idle state entered when the 82C37A has no valid DMA requests pending, at the end of a transfer sequence, ...
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DMA requests of the additional device to propagate through the priority network circuitry of the preceding device. The priority chain is preserved and the new device must wait for its turn to acknowledge requests. Since ...
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S24 state). It should be noted that an external EOP cannot cause the channel 0 Address and Word Count registers to autoinitialize, even if the Mode register is programmed for autoinitialization. An external EOP will autoinitialize the channel 1 registers, ...
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Current Word Count Register - Each channel has a 16-bit Current Word Count register. This register determines the number of transfers to be performed. The actual number of transfers will be one more than the number programmed in the Current ...
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Mask Register - Each channel has associated with it a mask bit which can be set to disable an incoming DREQ. Each mask bit is set when its associated channel produces an EOP if the channel is not programmed to ...
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Software Commands There are special software commands which can be executed by reading or writing to the 82C37A. These com- mands do not depend on the specific data pattern on the data bus, but are activated by the I/O operation ...
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Application Information Figure 6 shows an application for a DMA system utilizing the 82C37A DMA controller and the 80C88 Microprocessor. In this application, the 82C37A DMA controller is used to improve system performance by allowing an I/O device to transfer ...
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Figure 7 shows an application for a DMA system using the 82C37A DMA controller and the 80C286 Microprocessor. In this application, the system clock comes from the 82C284 clock generator PCLK signal which is inverted to provide proper READY setup ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications SYMBOL PARAMETER DMA (MASTER) MODE (1)TAEL AEN HIGH from CLK LOW (S1) Delay Time (2)TAET AEN LOW from CLK HIGH (SI) Delay Time (3)TAFAB ADR Active to Float Delay from CLK ...
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AC Electrical Specifications SYMBOL PARAMETER (21)TEPW EOP Pulse Width (22)TFAAB ADR Valid Delay from CLK HIGH (23)TFAC READ or WRITE Active from CLK HIGH (24)TFADB DB Valid Delay from CLK HIGH (25)THS HLDA Valid ...
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AC Electrical Specifications SYMBOL PARAMETER (62)TDVWL DACK Valid to WRITE LOW (63)TRHDI READ HIGH to DACK Inactive (64)TAZRL ADR Float to READ LOW PERIPHERAL (SLAVE) MODE (41)TAR ADR Valid or CS LOW to READ ...
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Timing Waveforms CS TCWL (43) IOW TAWL (42 DB0 - DB7 NOTE: Successive WRITE accesses to the 82C37A must allow at least TCY as recovery time between accesses. A TCY recovery time must be allowed before executing ...
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Timing Waveforms (Continued CLK TQS (30) DREQ TDQ (18) HRQ THS (25) HLDA TAEL AEN TCLSH (33) ADSTB DB0-DB7 A0-A7 DACK READ WRITE (FOR EXTENDED WRITE) INT EOP EXT EOP 82C37A ...
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Timing Waveforms (Continued) S0 S11 S12 CLK (33) (34) TCLSL TCLSH ADSTB TFAAB (22) TASS (11) A0-A7 TFADB (24) DB0-DB7 A8-A15 TDCL (15) TFAC (23) MEMR TFAC (23) MEMW EOP EXT EOP S2 CLK READ WRITE EXTENDED WRITE READY NOTE: ...
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Timing Waveforms (Continued) CLK A0-A7 READ WRITE READY V CC RESET IOR OR IOW AC Test Circuits V1 R1 OUTPUT FROM DEVICE UNDER TEST C1 (NOTE) NOTE: Includes STRAY and FIXTURE Capacitance TEST CONDITION DEFINITION TABLE PINS V1 All Outputs ...
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Burn-In Circuits VCC DO5 VCC/2 VCC/2 VCC/2 DO5 VCC/2 VCC/2 VCC/2 DO5 DO6 VCC/2 VCC/2 F12 F13 F14 F15 GND OPEN OPEN DO5 VCC/2 VCC/2 VCC/2 DO5 F1 D06 VCC/2 OPEN NOTES 5.5V 0. VIH ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...