CDP1822E Intersil Corporation, CDP1822E Datasheet

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CDP1822E

Manufacturer Part Number
CDP1822E
Description
256-Word x 4-Bit LSI Static RAM
Manufacturer
Intersil Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CDP1822E
Quantity:
294
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Low Operating Current
• Industry Standard Pinout
• Two Chip-Select Inputs-Simple Memory Expansion
• Memory Retention for Standby Battery Voltage of 2V
• Output-Disable for Common I/O Systems
• Three-State Data Output for Bus-Oriented Systems
• Separate Data Inputs and Outputs
Ordering Information
Pinout
CDP1822CE
CDP1822CEX CDP1822EX
CDP1822CD
CDP1822CDX
- V
Minimum
5V
DD
= 5V, Cycle Time 1 s . . . . . . . . . . . . . . . . . . 8mA
CDP1822E
CDP1822D
DO1
V
DI1
DI2
A3
A2
A1
A0
A5
A6
A7
SS
10V
-
CDP1822, CDP1822C
10
11
1
2
3
4
5
6
7
8
9
(PDIP, SBDIP)
TOP VIEW
PACKAGE
SBDIP
|
PDIP
Burn-In
Burn-In
Copyright
22
21
20
19
18
17
16
15
14
13
12
-40
-40
TEMP. RANGE
©
V
A4
R/W
CS1
O. D.
CS2
DO4
DI4
DO3
DI3
DO2
o
o
Intersil Corporation 1999
C to +85
C to +85
DD
o
o
C
C
E22.4
E22.4
D22.4A
D22.4A
PKG.
NO.
6-11
Description
The CDP1822 and CDP1822C are 256-word by 4-bit static
random-access memories designed for use in memory sys-
tems where high speed, low operating current, and simplicity
in use are desirable. The CDP1822 features high speed and
a wide operating voltage range. Both types have separate
data inputs and outputs and utilize single power supplies of
4V to 6.5V for the CDP1822C and 4V to 10.5V for the
CDP1822.
Two Chip-Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output sys-
tems. The Output Disable input allows these RAMs to be
used in common data Input/Output systems by forcing the
output into a high-impedance state during a write operation
independent of the Chip-Select input condition. The output
assumes a high-impedance state when the Output Disable is
at high level or when the chip is deselected by CS1 and/or
CS2.
The high noise immunity of the CMOS technology is pre-
served in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
NOTE:
Logic 1 = High, Logic 0 = Low, X = Don’t Care.
Read
Write
Write
Standby
Standby
Output
Disable
MODE
SELECT
(CS
CHIP
X
X
1
0
0
0
1
1
)
OPERATIONAL MODES
SELECT
(CS
CHIP
X
X
2
1
1
1
0
CDP1822C
INPUTS
2
)
CDP1822,
DISABLE
OUTPUT
(OD)
X
X
0
0
1
1
256-Word x 4-Bit
LSI Static RAM
File Number
WRITE
READ/
(R/W)
X
X
X
1
0
0
Read
Data In
High
Imped-
ance
High
Imped-
ance
High
Imped-
ance
High
Imped-
ance
OUTPUT
1074.2

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CDP1822E Summary of contents

Page 1

... Minimum • Output-Disable for Common I/O Systems • Three-State Data Output for Bus-Oriented Systems • Separate Data Inputs and Outputs Ordering Information 5V 10V PACKAGE CDP1822CE CDP1822E PDIP CDP1822CEX CDP1822EX Burn-In CDP1822CD CDP1822D SBDIP CDP1822CDX - Burn-In Pinout CDP1822, CDP1822C (PDIP, SBDIP) TOP VIEW ...

Page 2

Absolute Maximum Ratings DC Supply Voltage Range (All Voltages Referenced to V Terminal) SS CDP1822 . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

Static Electrical Specifications V O PARAMETER SYMBOL (V) Operating Current I - DD1 (Note 2) - Three-State Output OUT Leakage Current 0, 10 Input Capacitance Output Capacitance C - OUT NOTES Typical ...

Page 4

CHIP-SELECT 1 CHIP-SELECT 2 OUTPUT DISABLE READ/WRITE DATA OUT IMPEDANCE Dynamic Electrical Specifications CONDITIONS PARAMETER Read Cycle Times (Figure 2) Write Cycle t WC Address Setup t AS Write Recovery t WR Write Width t WRW Input ...

Page 5

Dynamic Electrical Specifications CONDITIONS PARAMETER Chip-Select 1 Hold t CS1H Chip-Select 2 Hold t CS2H Output Disable Set-Up t ODS NOTES: 1. Time required by a limit device to allow for indicated function Typical values are for T ...

Page 6

Data Retention Specifications At T PARAMETER Min. Data Retention Voltage V DR Data Retention Quiescent Current I DD Chip Deselect to Data Retention Time t CDR Recovery to Normal Operation Time VDR Rise and Fall Time ...

Page 7

A0 † ROW 3 INPUT A1 BUFFERS † 2 AND A2 DECODERS † ALL ROWS 1 A3 DESELECT † 21 FUNCTION A4 † 9 DI1 † 11 DI2 (4) † 13 GATES DI3 † 15 DI4 ...

Page 8

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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