82562EZ Intel Corporation, 82562EZ Datasheet
82562EZ
Specifications of 82562EZ
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82562EZ Summary of contents
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... Mbps Platform LAN Connect (PLC) Networking Silicon Product Features IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control Link status interrupt capability XOR tree mode support 3-port LED support (speed, link and activity) ...
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... Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82562EZ may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... Nov 2004 1.4 Nov 2004 1.5 January 2005 Datasheet Networking Silicon — 82562EZ Description Initial release (Intel Secret) Update to Table 10 - Pin Assignments (Intel Secret) Added part number (Intel Confidential) Table 15- Pin assignments revised from Rev. 1.3 to Rev 2.0 Removed confidential status Updated signal names to match design guides and reference schematics. • ...
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... Overview ............................................................................................................... 1 1.2 Scope .................................................................................................................... 1 1.3 Features ................................................................................................................ 1 1.4 Reference Documents...........................................................................................2 2.0 82562EZ Architectural Overview........................................................................................ 3 3.0 82562EZ Signal Descriptions ............................................................................................. 5 3.1 Signal Type Definitions ......................................................................................... 5 3.2 Twisted Pair Ethernet (TPE) Pins ......................................................................... 5 3.3 External Bias Pins ................................................................................................ 5 3.4 Clock Pins ............................................................................................................ 6 3.5 Platform LAN Connect Interface Pins.................................................................... 6 3.6 LED Pins ...
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... LAN Connect Interface DC Specifications ............................................. 26 6.2.3 LED DC Specifications .......................................................................... 26 6.2.4 10BASE-T Voltage and Current DC Specifications ............................... 26 6.2.5 100BASE-TX Voltage and Current DC Specifications .......................... 27 7.0 82562EZ Test Port Functionality...................................................................................... 29 7.1 Asynchronous Test Mode ................................................................................... 29 7.2 Test Function Description ................................................................................... 29 8.0 Package and Pinout Information ...................................................................................... 31 8.1 Package Information ........................................................................................... 31 8 ...
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... Introduction 1.1 Overview The 82562EZ is a highly-integrated Platform LAN Connect device designed for 10 or 100 Mbps Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. ...
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... Combined Footprint LOM Design Guide, AP-434, Intel Corporation • 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide, AP-440, Intel Corporation • 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide, AP-444, Intel Corporation • 82562EZ(EX)/82551ER(IT) & 82541ER Combined Footprint LOM Design Guide, AP-456, Intel Corporation 2 Datasheet ...
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... Architectural Overview The 82562EZ is a highly integrated Platform LAN Connect device that combines a 10BASE-T and 100BASE-TX physical layer interfaces. The 82562EZ supports a single interface fully compliant with the IEEE 802.3 standard. Figure 1. 82562EZ Block Diagram RDN/RDP TDN/ TDP Four pins, test Enable (TESTEN), Test Clock (ISOL_TCK), Test Input (ISOL_TI), and Test Execute (ISOL_EXEC), define the general operation of the device ...
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... B RBIAS10 B a. Based on some board designs, RBIAS100 and RBIAS10 values may need to be increased/decreased to compensate for high/ low MDI transmit amplitude. See the 82562EZ(EX)/82551ER(IT) & 82541ER Combined Footprint LOM Design Guide for more information. Datasheet Description Input pin to the 82562EZ. ...
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... LAN Connect Transmit Data. The LAN Connect transmit pins are used to transfer data from the MAC device to the 82562EZ. These pins are used to move transmitted data and real time control and management data. They also transmit out of band control data from the MAC to the PHY. The pins should be fully synchronous to JCLK. ...
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... Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted high, and the 82562EZ advertises only 10BASE-T technology during Auto-Negotiation processes in this state. Otherwise, the 82562EZ advertises all of its technologies. Note: ADV10 has an internal pull-down resistor. Test Clock. The Test Clock signal sets the device into asynchronous test mode in conjunction with the Test Input, Test Execute and Test Enable pins (refer to “ ...
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... Networking Silicon 3.8 Power and Ground Connections Pin Name Type VCC DPS VSS DPS 8 Description Digital 3.3 V Power. These pins should be connected to the main digital power supply. Digital Ground. These pins should be connected to the main digital ground. Datasheet ...
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... Transmit Blocks The transmit subsection of the 82562EZ accepts 3 bit wide data from the LAN Connect unit. Another subsection passes data unconditionally to the 4B/5B encoder. The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5-bit-wide parallel symbols ...
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... The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The 82562EZ implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation. The cipher equation used is: ...
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... Transmit Framing The 82562EZ does not differentiate between the fields of the MAC frame containing preamble, start of frame delimiter, data and Cyclic Redundancy Check (CRC). The 82562 encodes the first byte of the preamble as the “JK” symbol, encodes all other pieces of data according to the 4B/5B lookup table, and adds the “TR” code after the end of the packet ...
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... Register (LFSR) during an idle phase. The data is decoded at the 4B/5B decoder. After the 4B symbols are obtained, the 82562EZ outputs the receive data to the CSMA unit. In 100BASE-TX mode, the 82562EZ can detect errors in receive data in a number of ways. Any of the following conditions is considered an error: • ...
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... In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The filter is implemented inside the 82562EZ for supporting single magnetics that are shared with the 100BASE-TX side. The input differential voltage range for the Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3 ...
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... Auto Plugging Detection The 82562EZ senses the link all the time detects loss of any link activity for more than 6.6 seconds, it indicates to the Media Access Controller (MAC) an “unplugged state” by resetting the SQL LAN Connect control bit. If the 82562EZ is in reduced power mode and link activity is detected, the 82562EZ notifies the MAC (in less than 1 second) that “ ...
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... The 82562EZ can enter a reduced power state manually through bit 11 of register 0. This bit is ORed with the LAN Connect power down bit, which allows the 82562EZ to enter a reduced power state. Table 4. Register 0: Control Data Bit 11 Reduced Power Down 4.5 Reset When 82562EZ’s Reset signal (RSTSYNC) is asserted for at least 500 µseconds, all internal circuits are reset. The 82562EZ can also be reset through the MII management register reset bit (register 0, bit 15) ...
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... Enable 11 Reduced Power Down Datasheet Networking Silicon — 82562EZ Description This bit sets the status and control register of the PHY to their default states and is self-clearing. The PHY returns a value of one until the reset process has completed and accepts a read or write transaction. ...
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... When the PHY is placed in Loopback mode, the behavior of the PHY shall not be affected by the status of this bit Half Duplex 1 = Full Duplex This bit is not used in the 82562EZ and has a default value of 1b. ( used in other devices, it forces a colli- sion in response to the assertion of the transmit enable signal.) These bits are reserved and should be set to 0000000b ...
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... Reserved 13 Remote Fault 12:5 Technology Abil- ity Field Datasheet Networking Silicon — 82562EZ Description This bit reflects status of the Auto-Negotiation pro- cess Auto-Negotiation process has not completed 1 = Auto-Negotiation process completed remote fault condition detected 1 = Remote fault condition detected This bit reflects the PHY’s Auto-Negotiation ability sta- tus ...
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... Description This bit reflects the PHY’s link partner’s Next Page ability. This bit is used to indicate that the 82562EZ has suc- cessfully received its link partner’s Auto-Negotiation advertising ability. This bit reflects the PHY’s link partner’s Remote Fault condition. This bit reflects the PHY’ ...
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... Force Transmit H- Pattern 12 Force 34 Transmit Pattern Datasheet Networking Silicon — 82562EZ Description These bits are reserved and should be set to 00b. This bit disables the automatic reduced power down Enable automatic reduced power down 1 = Disable automatic reduced power down This bit is reserved and should be set to 0b. ...
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... Networking Silicon Bit(s) Name 11 Valid Link 10 Symbol Error Enable 9 Carrier Sense Disable 8 Disable Dynamic Power-Down 7 Auto-Negotiation Loopback 6 MDI Tri-State 5 Force Polarity 4 Auto Polarity Dis- able 3 Squelch Disable 2 Extended Squelch 1 Link Integrity Dis- able 0 Jabber Function Disable 5.3.3 Register 18: PHY Address Register ...
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... Definitions Bit(s) Name 15:0 End of Frame Counter Datasheet Networking Silicon — 82562EZ Description This field contains a 16-bit counter that increments for each disconnect event. The counter stops when it is full and self-clears on read Description This field contains a 16-bit counter that increments ...
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... Networking Silicon 5.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions Bit(s) Name 15:0 Jabber Detect Counter 5.3.11 Register 27: PHY Unit Special Control Bit Definitions Bit(s) Name 15:6 Reserved 5 Switch Probe Mapping 4 Reserved 3 100BASE-TX Receive Jabber Disable 2:0 LED Switch Con- ...
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... Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 3.45 V Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V Stresses above the listed absolute maximum ratings may cause permanent damage to the 82562EZ device. This is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
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... Networking Silicon 6.2.2 LAN Connect Interface DC Specifications Table 8. LAN Connect Interface DC Specifications Symbol Parameter Input/Output V CCJ Supply Voltage V Input Low Voltage IL Input High V IH Voltage Input Leakage I IL Current Output Low V OL Voltage Output High V OH Voltage Input Pin ...
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... Reject Peak IDR100 Voltage Input Common V ICM100 Mode Voltage NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN. Datasheet Networking Silicon — 82562EZ Condition Min Typical MHz ≤ f ≤ 10 MHz 585 5 MHz ≤ f ≤ 10 MHz V CC/2 ...
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... Test Port Functionality The 82562EZ’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. 7.1 Asynchronous Test Mode An asynchronous test mode is supported for system level design use. The modes are selected through the use of the Test Port input pins (TESTEN, ISOL_TCK, ISOL_TI and ISOL_EXEC) in static combinations ...
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... Networking Silicon Table 14. XOR Tree Chain Order Chain Order XOR Tree Output TOUT The following pins are not included in the XOR Tree chain: X1, ISOL_TCK, ISOL_EXEC, ISOL_TI and TESTEN. 30 Chain 11 SPDLED# 12 LILED# Datasheet ...
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... Package and Pinout Information 8.1 Package Information The 82562EZ is a 196 Ball Grid Array (BGA) package. The package dimensions are shown in Figure 5. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Developer website.. Figure 5. Dimension Diagram for the 196-pin BGA Note: No changes to existing soldering processes are needed for the 0 ...
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... Pinout Information Note: The power (VCC) and ground (VSS) pins have not been finalized and are subject to change. Do not finalize a design with this information. Revised information will be published when the product is available. Table 15. 82562EZ Pin Assignments Pin Pin Name Number A1 ...
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... Table 15. 82562EZ Pin Assignments Pin Pin Name Number C10 VSS C11 ACTLED# C12 VSSA C13 TDP C14 TDN VSS D5 VSS D6 VSS D7 VSS D8 VSS D9 NC D10 ISOL_EXEC D11 NC D12 ISOL_TI D13 VSSA D14 ISOL_TCK Datasheet Pin Pin Pin Name Number Number G5 VCCR ...
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... Networking Silicon Figure 6. 82562EZ Pin Out Diagram (Thru-the-Top View VCC VSS VSS 7 VCC VCCT SPDLED# ACTLED VSSA LILED# TOUT 13 TESTEN RBIAS100 14 NC RBIAS10 TDN VCC VSS VSS NC VSS VSS NC NC VSS VSS VSS VCCR NC VCCR VSS VSS NC VSS VCC ...