DD28F032SA-150 Intel Corporation, DD28F032SA-150 Datasheet
DD28F032SA-150
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DD28F032SA-150 Summary of contents
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... Intel’s DD28F032SA 32-Mbit FlashFile™ memory is a revolutionary architecture which enables the design of truly mobile, high performance, personal computing and communication products. With innovative capabilities, low power operation and very high read/program performance, the DD28F032SA is also the ideal choice for designing embedded mass storage flash memory systems. ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 COPYRIGHT © INTEL CORPORATION, 1996 CG-041493 ...
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... AC Characteristics for Page Buffer Write Operations ...................................................41 6.11 Erase and Word/Byte Program Performance, Cycling Performance and Suspend Latency .........................................44 7.0 DERATING CURVES ....................................45 8.0 MECHANICAL SPECIFICATIONS ................47 APPENDIX A: Device Nomenclature/ Ordering Information .....................................48 APPENDIX B: Additional Information...............49 DD28F032SA PAGE = 3.3V ± 0.3V) ..... 5.0V ± 0.5V) ....26 CC #—Controlled X 3 ...
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... DD28F032SA REVISION HISTORY Number -001 —Original Version -002 —Never Published -003 —Full Datasheet with Specifications — control 28F016SA No — control 28F016SA No -004 —DC Characteristics (3.3V V —Full Chip Erase Time (3.3V V —Full Chip Erase Time (5.0V V —Section 6.7: Added specifications t —TSOP dimension ...
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... PRODUCT OVERVIEW The DD28F032SA is a high-performance 32-Mbit (33,554,432-bit) block erasable nonvolatile random access memory organized as either 2 Mword x 16 Mbyte x 8. The DD28F032SA is built using two 28F016SA chips encapsulated in a single 56- lead TSOP Type I package. The DD28F032SA includes sixty-four 64-KB (65,536) blocks or sixty- four 32-KW (32,768) blocks ...
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... A order address and address A any care). A device block diagram is shown in Figure 1 . The DD28F032SA is specified for a maximum access time (4.75V to 5.25V) over the commercial temperature range (0° +70° C). A corresponding maximum access time of 150 ns at 3.3V (3.0V to 3.6V and 0° ...
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... E DQ 8-15 Output Buffer Input Buffer Y Decoder Address Queue Latches X Decoder Address Counter Figure 1. Block Diagram of 16-Mbit Devices in DD28F032SA Architectural Evolution Includes Page Buffers, Queue Registers and Extended Registers DQ 0-7 Output Input Input Buffer Buffer Buffer Data Queue Registers ID Register CSR ...
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... DD28F032SA 2.1 Lead Descriptions Symbol Type A INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when 0 device mode. This address is latched in x8 data programs. Not used in x16 mode (i.e., the A high). A –A INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block. ...
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... Do not leave any power pins floating. GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating CONNECT: Lead may be driven or left floating. Name and Function , and DQ float. Address A selects between 0-7 8-15 0 input buffer. Address A then becomes the lowest order 0 1 NOTES: DD28F032SA 9 ...
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... No DPD DPD X Standby Standby 1 Standby Active 0 Active Standby 1 Standby Standby 0 Illegal Condition E 28F016SA 28F016SV WP# WP# WP# WE# WE# WE# OE# OE# OE# RY/BY# RY/BY# RY/BY GND GND GND GND GND GND BYTE# BYTE# BYTE 0490_02 DD28F032SA Chip DPD Standby Active Active Standby ...
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... Block 040000 03FFFF 64-Kbyte Block 030000 02FFFF 64-Kbyte Block 020000 01FFFF 64-Kbyte Block 010000 00FFFF 64-Kbyte Block 000000 28F016SA No. 1 Figure 3. DD28F032SA Memory Map (Byte-Wide Mode) 1FFFFF 31 64-Kbyte Block 63 1F0000 1EFFFF 30 64-Kbyte Block 62 1E0000 1DFFFF 29 64-Kbyte Block 61 1D0000 1CFFFF ...
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... DD28F032SA 4.1 Extended Status Registers Memory Map for Either 28F016SA No 28F016SA No MODE A[20-0] 1F0006H RESERVED 1F0005H GSR 1F0004H RESERVED 1F0003H BSR 31 1F0002H RESERVED 1F0001H RESERVED 1F0000H . . . 010002H RESERVED 000006H RESERVED 000005H GSR 000004H RESERVED 000003H BSR 0 000002H RESERVED 000001H RESERVED 000000H Figure 4 ...
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... through a resistor. RY/BY independent of OE# while a WSM OH and A 0 until all operations are complete. RY/BY# goes to OL DD28F032SA DQ RY/BY# 0– OUT High Z X High Z X High 0089H V OH 66A0H RY/BY# 0– OUT High Z X High Z X High 89H V OH A0H V OH ...
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... DD28F032SA 5.3 28F008SA Compatible Mode Command Bus Definitions Command Notes Read Array Intelligent Identifier Read Compatible Status Register Clear Status Register Word/Byte Program Alternate Word/Byte Program Block Erase/Confirm Erase Suspend/Resume ADDRESS A = Array Address BA = Block Address IA = Identifier Address PA = Program Address X = Don’t Care NOTES: 1 ...
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... X xxF0H X xx80H DATA AD = Array Data WC (L,H) = Word Count (Low, High Page Buffer Data BC (L,H) = Byte Count (Low, High) BSRD = BSR Data WD (L,H) = Write Data (Low, High) GSRD = GSR Data DD28F032SA Third Bus Cycle Addr Data X BCH X WCH PA BC(H,L) PA WCH PA WD(H,L) ...
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... BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1. 11. To ensure that the DD28F032SA’s power consumption during sleep mode reads the dee p power-down current level, the system also needs to de-select the chip by taking either or both CE 12. The upper byte of the data bus (DQ ) during command programs is a “ ...
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... Status bit (OSS or DOS) is checked for success. If operation currently running, then GSR device pending sleep, then GSR Operation aborted: unsuccessful due to Abort command. Each 28F016SA device contains two Page Buffers. Selected Page Buffer is currently busy with WSM operation DD28F032SA PBSS 0 17 ...
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... DD28F032SA 5.7 Block Status Register BS BLS BOS BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy BSR.6 = BLOCK LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase BSR.5 = BLOCK OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running BSR.4 = BLOCK OPERATION ABORT STATUS 1 = Operation Aborted ...
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... Output shorted for no more than one second. No more than one output shorted at a time. 5. This specification also applies to pins marked “NC.” specifications refer to the DD28F032SA-070 in its High Speed Test configuration. CC NOTICE: This is a production datasheet. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design ...
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... DD28F032SA 6.2 Capacitance For a 3.3V System: Symbol Parameter C Capacitance Looking into an IN Address/Control Pin C Capacitance Looking into an OUT Output Pin C Load Capacitance Driven by LOAD Outputs for Timing Specifications Equivalent Load Timing Circuit For a 5.0V System: Symbol Parameter C Capacitance Looking into an IN ...
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... Data Outputs (Chip Enable BYTE# (Byte Enable) G OE# (Output Enable) W WE# (Write Enable) P RP# (Deep Power-Down Pin) R RY/BY# (Ready Busy) V Any Voltage Level Y 3/5# Pin 4.5V Minimum 3.0V Minimum CC DD28F032SA Pin States H High L Low V Valid X Driven, but not necessarily valid Z High Impedance 21 ...
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... AC test inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0.” Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns. Figure 7. Transient Input/Output Reference Waveform (V and High Speed Reference Waveform NOTES: 1. Testing characteristics for DD28F032SA-080/DD28F032SA-100. 2. Testing characteristics for DD28F032SA-070/DD28F032SA-150. 22 2.0 OUTPUT TEST POINTS 0.8 (0.45 VTTL) for a Logic “ ...
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... From Output under Test Total Capacitance = 50 pF Figure 9. Transient Equivalent Testing Load Circuit (V 2 From Output under Test Total Capacitance = 30 pF Figure 10. High Speed Transient Equivalent Testing Load Circuit (V DD28F032SA Test Point = 5.0V ± 10%) CC Transmission Line Test Point = 3.3V ± 0.3V) ...
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... DD28F032SA 6.4 DC Characteristics V = 3.3V ± 0.3V 0°C to +70° 3/5# = Pin Set High for 3.3V Operations Symbol Parameter Notes I Input Load Current 1 IL Output Leakage Current V Standby I CC 1,5,6,8 CCS Current V Deep Power CCD Down Current Read Current 1,4,5,6 CCR Program ...
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... V 2 –2 – 0 –100 µA OH 0.0 6.5 V 11.4 12.0 12 3.3V 12.0V 25°C. These currents are and not guaranteed in the PP PPL to < static operation Standby Current to max and I CCR CCR CCW CCE DD28F032SA PPH PPH PPH Min CC Min CC Min CC . CCES 25 ...
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... DD28F032SA 6.5 DC Characteristics V = 5.0V ± 0.5V, 5.0V ± 0.25V 0°C to +70° 3/5# Pin Set Low for 5.0V Operations Symbol Parameter Notes I Input Load Current 1 IL Output Leakage Current I V Standby 1,5,6,8 CC CCS Current I V Deep Power CCD Down Current Read Current ...
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... V 11.4 12.0 12 5.0V 12.0V +25°C. These currents are and not guaranteed in the PP PPL to < static operation standby current. to max and I CCR CCR CCW CCE DD28F032SA # = PPH PPH PPH Min 5 Min –2 Min –100 µ CCES 27 ...
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... FLQV t FHQV t BYTE# Low to Output in High Z FLQZ Low to BYTE# High or Low ELFL X t ELFH For Extended Status Register Reads t Address Setup Going Low AVEL X t Address Setup to OE# Going Low AVGL 28 (1) DD28F032SA-150 Notes Min Max 150 150 2 150 750 150 ...
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... For Extended Status Register Reads t Address Setup to 3,4 AVEL CE # Going Low X t Address Setup to 3,4 AVGL OE# Going Low (1) (Continued) DD28F032SA - 070 (6) DD28F032SA DD28F032SA - (7) 080 100 Min Max Min Max Min 70 80 100 400 480 DD28F032SA Units - (7) Max ns 100 ns 100 ns 550 100 ...
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... DD28F032SA NOTES: 1. See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7. 2. OE# may be delayed after the falling edge of CE ELQV GLQV 3. Sampled, not 100% tested. 4. This timing parameter is used to latch the correct BSR data onto the outputs. 5. Device speeds are defined as: 70/ ...
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... CE X Figure 12. BYTE# Timing Waveforms ADDRESSES STABLE t AVAV FLQV AVQV t GLQV t t ELQV DATA DATA OUTPUT OUTPUT t FLQZ HIGH Z DATA OUTPUT # going low, or the first going low, or the first DD28F032SA t EHQZ t GHQZ OH HIGH Z 0490-12 # going high going high ...
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... YLPH YHPH PHEL3 PHEL5 2. The power supply may start to switch concurrently with RP# going low. 3. The address access time and RP# high to data valid time are shown for the DD28F032SA-80 and 5.0V V Refer to the AC Characteristics-Read Only Operations for 3. YLPH 5.0V ...
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... Write Recovery before Read WHGL t V Hold from Valid Status Register QVVL PP (CSR, GSR, BSR) Data and RY/BY# High t 1 Duration of Word/Byte Program Operation WHQV t 2 Duration of Block Erase Operation WHQV DD28F032SA (1) DD28F032SA-150 Notes Min Typ Max Unit 150 ns 3 100 ns 480 2 ...
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... Address Hold WHAX from WE# High CE # Hold WHEH from WE# High WE# Pulse t 30 WHWL Width High Read t 0 GHWL Recovery before Write WE# High to t WHRL RY/BY# Going Low 34 DD28F032SA-080 DD28F032SA-100 Typ Max Min Typ Max Min 80 100 100 100 480 480 100 100 ...
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... This information will be available in a technical paper. Please call Intel’s Applications Hotline or your local sales office for more information. DD28F032SA-080 DD28F032SA-100 Typ Max Min Typ Max Min Typ Note 4.5 6 Note 4 0 going low or the first going high going low or the first going high DD28F032SA (1) Unit Max ns µs ns µs 6 Note µ sec 35 ...
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... DD28F032SA WRITE VALID ADDRESS DEEP WRITE DATA-WRITE OR & DATA (DATA-WRITE) OR POWER-DOWN ERASE SETUP COMMAND ERASE CONFIRM COMMAND V IH ADDRESSES ( NOTE AVAV t AVWH V IH ADDRESSES ( NOTE AVAV AVWH V IH CEx # (E) V NOTE ELWL WHEH V IH OE# ( WHWL V IH WE# ( WLWH t t DVWH WHDX V IH ...
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... Write Recovery before Read EHGL t V Hold from Valid Status Register QVVL PP (CSR, GSR, BSR) Data and RY/BY# High t 1 Duration of Word/Byte Program Operation EHQV t 2 Duration of Block Erase Operation EHQV DD28F032SA (1) DD28F032SA-150 Notes Min Typ Max Unit 150 ns 3 100 ns 480 2 ...
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... X 30 EHEL Width High Read t 0 GHEL Recovery before Write CE # High EHRL RY/BY# Going Low RP# Hold from RHPL Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 38 DD28F032SA-080 DD28F032SA-100 Typ Max Min Typ Max Min 80 100 100 100 480 480 ...
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... DD28F032SA-080 DD28F032SA-100 Typ Max Min Typ Max Min Note 4.5 6 Note 4 0 going low or the first going high going low or the first going high for all command write operations. X DD28F032SA (1) Unit Typ Max µs ns µs 6 Note µ sec 39 ...
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... DD28F032SA WRITE VALID ADDRESS DEEP WRITE DATA-WRITE OR & DATA (DATA-WRITE) OR POWER-DOWN ERASE SETUP COMMAND ERASE CONFIRM COMMAND V IH ADDRESSES ( NOTE AVAV t AVEH V IH ADDRESSES ( NOTE AVAV AVEH V IH WE# ( WLEL EHWH V IH OE# ( EHEL V IH CEx#( NOTE 4 t ELEH t t DVEH EHDX V IH ...
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... WE# Pulse Width WLWH t Data Hold from WE# High WHDX t Address Hold from WE# High WHAX Hold from WE# High WHEH X t WE# Pulse Width High WHWL t Read Recovery before Write GHWL t Write Recovery before Read WHGL DD28F032SA (1) DD28F032SA-150 Notes Min Typ Max Unit 150 ...
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... CE X For 28F016SA No defined as the latter These are WE#-controlled write timings, equivalent CE 2. Sampled, not 100% tested. 3. Address must be valid during the entire WE# low pulse or the entire CE 42 (1) (Continued) DD28F032SA-080 DD28F032SA-100 Typ Max Min Typ Max Min Typ 80 100 0 0 ...
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... CEx# ( ELWL V IH WE# ( AVWL V IH ADDRESSES ( HIGH Z DATA (D/ Figure 16. Page Buffer Write Timing Waveforms (Loading Data to the Page Buffer) t WHEH t WHWL t WLWH t WHAX VALID t t DVWH WHDX D IN DD28F032SA 0490-16 43 ...
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... DD28F032SA 6.11 Erase and Word/Byte Write Performance, Cycling Performance (3) and Suspend Latency V = 3.3V ± 0.3V 12.0V ± 0.6V Sym Parameter Page Buffer Byte Write Time Page Buffer Word Write Time t 1 Word/Byte Program Time 2 WHRH t 2 Block Program Time WHRH t 3 Block Program Time ...
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... E 7.0 DERATING CURVES 290489-16.eps Figure 17. I vs. Frequency (V = 5.5V) for x16 Operation 290489-18.eps Figure 18. I during Block Erase CC DD28F032SA 290489-19.eps Figure 19. I vs. Frequency (V = 3.6V) for x16 Operation 290489-21.eps Figure 20. I during Block Erase PP 45 ...
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... DD28F032SA Figure 21. Access Time (t 290489-25.eps Figure 22. I during Word Write Operation 290489-24.eps ) vs. Output Loading ACC 290490-26.eps Figure 23. I during Page Buffer Write PP Operation ...
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... D 19.80 L 0.500 N 0° 0.150 A2 SEE DETAIL SEATING PLANE A DETAIL A C Ø L Millimeters Nominal Maximum 1.20 0.995 1.025 0.150 0.200 0.125 0.135 18.40 18.60 14.00 14.20 0.50 20.00 20.20 0.600 0.700 56 3° 5° 0.100 0.250 0.350 DD28F032SA Y 290490-26 Notes 47 ...
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... DD28F032SA DEVICE NOMENCLATURE/ORDERING INFORMATION DUAL DIE NOTES: Two valid combinations of speeds exist: DD28F032SA-070, DD28F032SA-080, DD28F032SA-150 or DD28F032SA-100, DD28F032SA-150 Option Order Code 1 DD28F032SA-070 2 DD28F032SA-100 48 APPENDIX ACCESS SPEED (ns 100 ns Valid Combinations ± 0.3V ± 5 DD28F032SA-150 DD28F032SA-070 DD28F032SA-150 5.0V CC ± 10%, 100 pF DD28F032SA-080 DD28F032SA-100 ...
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... NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools. APPENDIX B (1,2) Document/Tool DD28F032SA 49 ...