CA3310M Intersil Corporation, CA3310M Datasheet
CA3310M
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CA3310M Summary of contents
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... The clock may also be driven from an external source. Ordering Information PART LINEARITY NUMBER (INL, DNL) CA3310E 0.75 LSB CA3310AE 0.5 LSB CA3310M 0.75 LSB CA3310AM 0.5 LSB CA3310D 0.75 LSB CA3310AD 0.5 LSB CA3310, CA3310A (PDIP, SBDIP, SOIC) TOP VIEW ...
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Functional Block Diagram V DD ALL LOGIC 16C REF 8C 50 SUBSTRATE RESISTANCE 16C REF ...
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Typical Application Schematics 8 100 10 ICL7663S 6 ADJUST GAIN 100 0 CA3140 - - R4 10K 1 4 0.1 A -1V 100 ...
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Absolute Maximum Ratings Digital Supply Voltage Analog Supply Voltage ( ...
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Electrical Specifications Unless Otherwise Specified (Continued) PARAMETER DIGITAL OUTPUTS D0 - D9, DRDY High-Level Output Voltage Low-Level Output Voltage Three-State Leakage Output Capacitance CLK OUTPUT High-Level Output Voltage Low-Level Output Voltage TIMING Clock Frequency Clock Pulse ...
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Timing Diagrams 1 CLK t DRDY D1 DRDY t DATA INPUT FIGURE 1. FREE RUNNING, STRT TIED LOW, DRST TIED HIGH OEL OR OEM D2- D9 OFF TO HIGH OFF TO LOW ...
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Timing Diagrams (Continued) 13 CLK (EXTERNAL) xxxxxxx xxxxxxx xxxxxxx STRT xxxxxxx DRDY HOLD INPUT FIGURE 4. STRT PULSED LOW, DRST TIED HIGH, EXTERNAL CLOCK (INTERNAL EXTERNAL) DRST DRDY Typical Performances Curves 800 V DD 700 ...
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Typical Performances Curves + REF +60 +40 (+) I PEAK + -20 (-) I PEAK - INPUT ...
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Typical Performances Curves REF LOAD = 50pF/OUTPUT 10 CONTINUOUS CONVERSIONS 0.5 1.0 1.5 2.0 CLOCK FREQUENCY (MHz) FIGURE 14. SUPPLY ...
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Device Operation The CA3310 is a CMOS 10-bit, analog-to-digital converter that uses capacitor-charge balancing to successively approximate the analog input. A binarily weighted capacitor network forms the D-to-A “Heart” of the device. See the Functional Diagram of the CA3310. The ...
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The input will continue to track the DRDY output will remain high during this time. A low signal applied to STRT (at least t now initiate a new conversion. The STRT signal (after ...
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OUTPUT CODE (HEX) 001 000 OFFSET POINT FIGURE 19. NORMALIZED GAIN, OFFSET, INTEGRAL AND DIFFERENTIAL LINEARITY ERRORS vs REFERENCE VOLTAGE CA3310, CA3310A EXPECTED TRANSFER CURVE OFFSET ERROR 1 2 1022 1024 1024 ...
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Other Accuracy Effects Linearity, offset, and gain errors are dependent on the magnitude of the full-scale input range, V Figure 11 shows how these errors vary with full-scale range. The clocking speed is a second factor that affects conversion accuracy. ...
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Single +5V Supply If only a single +5V supply is available, an ICL7660 can be used to provide approximately +8V and -4V to the opera- tional amplifier. Figure 20 shows this approach. Note that the converter and associated capacitors should ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...