X25020 Intersil Corporation, X25020 Datasheet

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X25020

Manufacturer Part Number
X25020
Description
Manufacturer
Intersil Corporation
Datasheet

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X25020
2K
FEATURES
FUNCTIONAL DIAGRAM
Direct Write
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3834-1.8 6/10/96 T3/C1/D0 NS
1MHz Clock Rate
SPI Modes (0,0 & 1,1)
256 X 8 Bits
—4 Byte Page Mode
Low Power CMOS
—10 A Standby Current
—3mA Active Write Current
2.7V To 5.5V Power Supply
Block Lock Protection
—Protect 1/4, 1/2 or all of E
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
8-Lead PDlP Package
8-Lead SOIC Package
AN9 • AN18 • AN31 • AN37 • AN40
and Block Lock
A V A I L A B L E
A
PPLICATION
HOLD
SCK
SO
WP
CS
SI
SPI Serial E
Protection is a trademark of Xicor, Inc.
N
OTES
COMMAND
REGISTER
CONTROL
CONTROL
DECODE
STATUS
TIMING
LOGIC
WRITE
LOGIC
AND
AND
2
PROM Array
2
PROM with Block Lock
PROTECT
WRITE
LOGIC
X25020
1
DESCRIPTION
The X25020 is a CMOS 2048-bit serial E
nally organized as 256 x 8. The X25020 features a serial
interface and software protocol allowing operation on a
simple three-wire bus. The bus signals are a clock input
(SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a chip select
(CS) input, allowing any number of devices to share the
same bus.
The X25020 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25020 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25020 disabling all write attempts, thus providing
a mechanism for limiting end user capability of altering
the memory.
The X25020 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
X DECODE
LOGIC
TM
Protection
16
16
32
Characteristics subject to change without notice
4
DATA REGISTER
Y DECODE
256 BYTE
ARRAY
16 X 32
16 X 32
32 X 32
8
256 x 8 Bit
2
PROM, inter-
3834 FHD F01

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X25020 Summary of contents

Page 1

... PROM with Block Lock DESCRIPTION The X25020 is a CMOS 2048-bit serial E nally organized as 256 x 8. The X25020 features a serial interface and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. ...

Page 2

... When WP is held HIGH, all functions, including nonvola- tile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25020. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. ...

Page 3

... WIP are read-only and automatically set by other operations. The Write-In-Process (WIP) bit indicates whether the X25020 is busy with a write operation. When set to a “1”, a write is in progress, when set to a “0”, no write is in progress. During a write, all other bits are set to “1”. ...

Page 4

... CS must go LOW and remain LOW for the duration of the operation. The host may continue to write bytes of data to the X25020. The only restriction is that the 4 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “ ...

Page 5

... X25020 Operational Notes The X25020 powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition required to enter an active state and receive an instruction. • SO pin is high impedance. • The “write enable” latch is reset. ...

Page 6

... X25020 Figure 3. Write Enable Latch Sequence CS SCK SI SO Figure 4. Byte Write Operation Sequence SCK INSTRUCTION SI HIGH IMPEDANCE HIGH IMPEDANCE BYTE ADDRESS 3834 ILL F05 ...

Page 7

... X25020 Figure 5. Page Write Operation Sequence SCK INSTRUCTION SCK DATA BYTE Figure 6. Write Status Register Operation Sequence CS 0 SCK SI HIGH IMPEDANCE ...

Page 8

... – 0 5V. CC Test 8 Limits X25020 5V 10% X25020– 5.5V X25020–2.7 2.7V to 5.5V Test Conditions SCK = V x 0.1/V x 0.9 @ 1MHz Open OUT SS CC ...

Page 9

... X25020 EQUIVALENT A.C. LOAD CIRCUIT 2.16K OUTPUT 3.07K A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Symbol Parameter f Clock Frequency SCK t Cycle Time CYC CS Lead Time t LEAD CS Lag Time t LAG t Clock HIGH Time WH t Clock LOW Time ...

Page 10

... X25020 Serial Output Timing CS SCK MSB OUT ADDR SI LSB IN Serial Input Timing CS t LEAD SCK MSB IN HIGH IMPEDANCE CYC MSB–1 OUT LAG DIS LSB OUT 3834 FHD F09 LAG t FI LSB IN ...

Page 11

... X25020 Hold Timing CS SCK SO SI HOLD SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A 11 3834 FHD F11 OUTPUTS Will be steady Will change ...

Page 12

... X25020 PACKAGING INFORMATION HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) PIN 1 INDEX PIN 1 0.300 (7.62) REF. SEATING PLANE 0.150 (3.81) 0.125 (3.18) ...

Page 13

... X25020 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0 – 8 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.150 (3.80) 0.158 (4.00) PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7 0.004 (0.19) 0.050 (1.27) 0.010 (0.25 0.0075 (0.19) 0.250" 0.010 (0.25) ...

Page 14

... Temperature Range Blank = Commercial = + Industrial = – +85 C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC X25020 X Blank = 8-Lead SOIC P = 8-Lead Plastic DIP X Blank = 10%, – + 5.5V + 5.5V, – + 2.7V to 5.5V + 2.7V to 5.5V, – ...

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