CS82C50A-5 Intersil Corporation, CS82C50A-5 Datasheet
CS82C50A-5
Available stocks
Related parts for CS82C50A-5
CS82C50A-5 Summary of contents
Page 1
... Loopback and Echo Modes • Doubled Buffered Transmitter and Receiver • Single 5V Supply Ordering Information TEMPERATURE o PACKAGE RANGE ( C) PDIP 0 to +70 CP82C50A-5 -40 to +85 IP82C50A-5 PLCC 0 to +70 CS82C50A-5 -40 to +85 IS82C50A-5 CERDIP 0 to +70 CD82C50A-5 -40 to +85 ID82C50A-5 -55 to +125 MD82C50A-5/B Functional Diagram MICROPROCESSOR INTERFACE CSO 12 CS1 13 ...
Page 2
Pinouts RCLK SOUT BAUDOUT 82C50A 82C50A (PDIP, CERDIP) TOP VIEW RCLK 9 32 SIN 10 31 ...
Page 3
Pin Description PIN SYMBOL NUMBER TYPE DISTR DISTR 21 I DOSTR DOSTR 18 I D0-D7 1-8 I/O A0, A1, 28, 27 XTAL1 XTAL2 17 O SOUT 11 O GND 20 ...
Page 4
Pin Description (Continued) PIN SYMBOL NUMBER TYPE RTS 32 O BAUDOUT 15 O OUT1 34 O OUT2 DCD lNTRPT 30 O SIN 10 I 82C50A ACTIVE LEVEL L REQUEST TO ...
Page 5
Pin Description (Continued) PIN SYMBOL NUMBER TYPE CS0, CS1, 12,13, I CS2 CSOUT 24 O DDIS 23 O ADS 25 I RCLK 9 I Block Diagram ( DATA BUS BUFFER D7 ...
Page 6
Accessible Registers The three types of internal registers in the 82C50A used in the operation of the device are control, status, and data registers. The control registers are the Bit Rate Select Register DLL and DLM, Line Control Register, Interrupt ...
Page 7
LINE CONTROL REGISTER (LCR) The format of the data character is controlled by the Line Control Register. The contents of the LCR may be read, eliminating the need for separate storage of the line charac- teristics in system memory. The ...
Page 8
LSR BITS 0 THRU 7 LSR (0) Data Ready (DR) LSR (1) Overrun Error (OE) LSR (2) Parity Error (PE) LSR (3) Framing Error (FE) LSR (4) Break Interrupt (BI) LSR (5) Transmitter Holding Register Empty (THRE) LSR (6) Transmitter ...
Page 9
Serial Output (SOUT) is set to the marking (logic 1) state, and the receiver data input Serial Input (SIN) is discon- nected. The output of the Transmitter Shift Register is looped back into the Receiver Shift Register input. The four ...
Page 10
MSR(4) is equivalent to RTS in the MCR. MSR(5) Data Set Ready (DSR): Data Set Ready (DSR status of the DSR input (Pin-37) from the modem to the 82C50A which indicates that the modem ...
Page 11
TRANSMITTER HOLDING REGISTER (THR) The Transmitter Holding Register (THR) holds parallel data from the data bus (D0-D7) until the Transmitter Shift Register is empty and ready to accept a new character for transmis- sion. The transmitter and receiver word length ...
Page 12
Modem Status Registers. The contents of the Interrupt Enable Register are indicated in Table 3 and are described below. IER(0): When programmed high (IER(0) = Logic 1), IER(0) enables Received Data Available interrupt. IER(1): When programmed high (IER(1) = Logic ...
Page 13
Transmitter The serial transmitter section consists of a Transmitter Hold- ing Register (THR), Transmitter Shift Register (TSR), and associated control logic. The Transmitter Holding Register Empty (THRE) and Transmitter Shift Register Empty (TEMT) are two bits in the Line Status ...
Page 14
TABLE 5. BAUD RATES USING 2.4576MHz CRYSTAL DESIRED DIVISOR USED TO BAUD GENERATE DIFFERENCE BETWEEN RATE 16 x CLOCK DESIRED AND ACTUAL 50 3072 75 2048 110 1396 134.5 1142 150 1024 300 512 600 256 1200 128 1800 85 ...
Page 15
TABLE 7. 82C50A RESET OPERATIONS (Continued) REGISTER/SIGNAL Out2 RTS DTR Out1 Programming The 82C50A is programmed by the control registers LCR, lER, DLL and DLM, and MCR. These control words define the character length, number of stop bits, parity, baud ...
Page 16
Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 17
AC Electrical Specifications V CC Timing Requirements SYMBOL PARAMETER (1) TAW Address Strobe Width (2) TAS Address Setup Time (3) TAH Address Hold Time (4) TCS Chip Select Setup Time (5) TCH Chip Select Hold Time (6) TDIW DISTR DlSTR ...
Page 18
AC Electrical Specifications V CC Timing (Continued) SYMBOL PARAMETER BAUD GENERATOR (29) N Baud Divisor (30) TBLD Baud Output Negative Edge Delay (31) TBHD Baud Output Positive Edge Delay (32) TLW Baud Output Down Time (33) THW Baud Output Up ...
Page 19
... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...
Page 20
Timing Waveforms (Continued) ADS (2) tAS A2, A1, A0 (4) tCS CS2, CS1, CS0 CSOUT DOSTR/DOSTR DISTR/DISTR DATA D0-D7 † Applicable only when ADS is tied low. ADS (2) tAS A2, A1, A0 (4) tCS CS2, CS1, CS0 CSOUT DISTR/DISTR ...
Page 21
Timing Waveforms (Continued) SAMPLE CLK SIN (RECEIVER INPUT DATA) SAMPLE CLK INTERRUPT (DATA READY OR RCVR ERR) DISTR/DISTR (READ REC DATA BUFFER OR ROLSR) NOTES: 1. See Write Cycle Timing. 2. See Read Cycle Timing. SERIAL OUT (SOUT) INTERRUPT (THRE) ...