HSP48410JC-33 Intersil Corporation, HSP48410JC-33 Datasheet

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HSP48410JC-33

Manufacturer Part Number
HSP48410JC-33
Description
Manufacturer
Intersil Corporation
Datasheet

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Histogrammer/Accumulating Buffer
The Intersil HSP48410 is an 84 lead Histogrammer IC
intended for use in image and signal analysis. The on-board
memory is configured as 1024 x 24 array. This translates to
a pixel resolution of 10 bits and an image size of 4k x 4k with
no possibility of overflow.
In addition to Histogramming, the HSP48410 can generate
and store the Cumulative Distribution Function for use in
Histogram Equalization applications. Other capabilities of
the HSP48410 include: Bin Accumulation, Look Up Table,
24-bit Delay Memory, and Delay and Subtract mode.
A Flash Clear pin is available in all modes of operation and
performs a single cycle reset on all locations of the internal
memory array and all internal data paths.
The HSP48410 includes a fully asynchronous interface
which provides a means for communications with a host,
such as a microprocessor. The interface includes dedicated
Read/Write pins and an address port which are
asynchronous to the system clock. This allows random
access of the Histogram Memory Array for analysis or
conditioning of the stored data.
Ordering Information
Block Diagram
HSP48410JC-33
HSP48410JC-40
HSP48410GC-33
HSP48410GC-40
PART NUMBER
IOADD0-9
DIN0-23
PIN0-9
24
10
10
RANGE (
TEMP.
0 to 70
0 to 70
0 to 70
0 to 70
GENERATOR
ADDRESS
o
C)
1
84 Ld PLCC
84 Ld PLCC
84 Ld PGA
84 Ld PGA
Data Sheet
PACKAGE
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
MUX
N84.1.15
N84.1.15
G84.A
G84.A
PKG.
NO.
ADDRESS
DATA
IN
HISTOGRAM
MEMORY
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
24
24
ARRAY
Features
• 10-Bit Pixel Data
• 4k x 4k Frame Sizes
• Asynchronous Flash Clear Pin
• Single Cycle Memory Clear
• Fully Asynchronous 16 or 24-Bit Host Interface
• Generates and Stores Cumulative Distribution Function
• Look Up Table Mode
• 1024 x 24-Bit Delay Memory
• 24-Bit Three State I/O Bus
• DC to 40MHz Clock Rate
Applications
• Histogramming
• Histogram Equalization
• Image and Signal Analysis
• Image Enhancement
• RGB Video Delay Line
DATA
OUT
24
May 1999
ADDER
File Number 3185.2
INTERACE
DIO
HSP48410
DIO0-23

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HSP48410JC-33 Summary of contents

Page 1

... Read/Write pins and an address port which are asynchronous to the system clock. This allows random access of the Histogram Memory Array for analysis or conditioning of the stored data. Ordering Information TEMP. o PART NUMBER RANGE ( C) PACKAGE HSP48410JC- PLCC HSP48410JC- PLCC HSP48410GC- PGA HSP48410GC- ...

Page 2

Pinouts 11 DIN8 DIN10 10 DIN5 DIN7 9 DIN4 DIN6 8 DIN2 DIN3 7 PIN9 DIN0 6 V DIN1 CC 5 PIN8 PIN7 4 PIN5 PIN4 3 PIN3 PIN1 2 PIN2 FC 1 PIN0 START PIN ‘A1’ ...

Page 3

Pinouts (Continued START FCT2 16 FCT1 17 FCT0 GND 20 UWS 21 IOADD9 22 IOADD8 23 IOADD7 24 IOADD6 25 IOADD5 26 IOADD4 27 IOADD3 28 IOADD2 29 IOADD1 30 ...

Page 4

Pin Description NAME PLCC PIN TYPE CLK 1 PIN0-9 3-11 FCT0-2 16-18 START DIN0-23 58-63, 65-82 DIO0-23 33-40, 42-57 IOADD0-9 22-31 UWS GND 20, 41, ...

Page 5

Functional Description The Histogrammer is intended for use in signal and image processing applications. The on-board RAM is 24 bits by 1024 locations. For histogramming, this translates to an image size with 10-bit data. A Functional ...

Page 6

Functional Block Diagram MUX DIN 0-23 IOADD 0-9 PIN 0-9 CLK WR RD UWS CONTROL START FC FCT 0-2 FUNCTION DECODE LD ALL REGISTERS ARE CLOCKED BY CLK Histogram Mode This is the fundamental operation for which this chip was ...

Page 7

Histogram Accumulate Mode This function is very similar to the Histogram function. In this case, a counter is used to provide the address data to the RAM. The RAM is sequentially accessed, and the data from each bin is added ...

Page 8

Look Up Table Mode A Look Up Table (LUT) is used to perform a fixed transformation function on pixel values. This is particularly useful when the transformation is nonlinear and cannot be realized directly with hardware. An example is the ...

Page 9

Delay and Subtract Mode This mode is similar to the Delay Memory mode, except the input data is subtracted from the corresponding data stored in RAM (See Figures 12 and 13). RAM DIN 0-23 IN OUT ADDRESS TWO’S COMPLEMENT CLK ...

Page 10

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11

AC Electrical Specifications V PARAMETER FCT0-2 Hold from LD START Setup to CLK START Hold from CLK PIN0-9 Setup Time PIN0-9 Hold Time LD Pulse Width LD Setup to START WR Low WR High Address Setup Address Hold DIO Setup ...

Page 12

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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