IS82C85 Intersil Corporation, IS82C85 Datasheet
IS82C85
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IS82C85 Summary of contents
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... Lead Slimline Dual-In-Line or 28 Pad Square LCC Package Options • Single 5V Power Supply • Operating Temperature Range - C82C85 . . . . . . . . . . . . . . . . . . . . . . . . . . 0 - I82C85 . . . . . . . . . . . . . . . . . . . . . . . . . -40 - M82C85 . . . . . . . . . . . . . . . . . . . . . . . -55 Ordering Information PART NUMBER PACKAGE TEMP. RANGE CS82C85 28 Ld PLCC 0 IS82C85 -40 CD82C85 24 Ld CERDIP 0 ID82C85 -40 MD82C85/B -55 MR82C85/B 28 Pad CLCC -55 Pinouts 24 LEAD CERDIP ...
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Pin Descriptions DIP PIN SYMBOL NUMBER TYPE CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections. The crystal frequency must be 3 times the maximum desired processor clock frequency the oscillator ...
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Pin Descriptions (Continued) DIP PIN SYMBOL NUMBER TYPE RES 17 I RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C85 provides a Schmitt trigger input so that an RC connection can be used ...
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Functional Description The 82C85 Static Clock Controller/Generator provides sim- ple and complete control static CMOS system operating modes. The 82C85 supports full speed, slow, stop-clock and stop-oscillator operation. While it is directly compatible with the Intersil 80C86 and 80C88 CMOS ...
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X1 Schmitt trigger input threshold voltage and 8192 cycles of the crystal oscillator output are counted by an internal counter. After this count is complete, the stopped outputs (CLK, CLK50, PCLK, and OSC) ...
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FAST mode operation is enabled by each of two conditions: • The SLO/FST input is HIGH and a START or reset command is issued • The SLO/FST input is held HIGH for at least 6 oscillator or EFI cycles. Alternate ...
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The 82C85 S2/STOP, S1 and S0 control lines were designed to detect a passive 111 state followed by a HALT 011 logic state before recognizing the HALT instruction and stopping the system clocks. In the MAXimum mode, the 80C86/88 status ...
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FAST command recognition. Proper CLK and CLK 50 phase relationships are maintained and minimum pulse width specifications are met. FAST-to-SLOW or SLOW-to-FAST mode changes will occur on the next rising or falling edge of PCLK important ...
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Clock Generator The clock generator consists of two synchronous divide-by- three counters with special clear inputs that inhibit the count- ing. One counter generates a 33% duty cycle waveform (CLK) and the other generates a 50% duty cycle waveform (CLK50). ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications V SYMBOL PARAMETER TIMING REQUIREMENTS (1) TEHEL External Frequency HIGH Time (2) TELEH External Frequency LOW Time (3) TELEL EFI or Crystal Period (4) TEFIDC External Frequency Input Duty Cycle (5) Fx Crystal Frequency (6) TR1VCL RDY1, ...
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AC Electrical Specifications V SYMBOL PARAMETER (27) TCLCH CLK LOW Time (28) T5CHCL CLK50 HIGH Time (29) T5CLCH CLK50 LOW Time (30) TCH1CH2 CLK/CLK50 Rise Time (31) TCL2CL1 CLK/CLK50 Fall Time (32) TPHPL PCLK HIGH Time (33) TPLPH PCLK LOW ...
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Timing Waveforms TELEL EFI I (1) TEHEL OSC 0 CLK 0 CLK50 0 PCLK 0 (15) TEHYL CSYNC I (16) TYHYL NOTE: All Timing Measurements are made at 1.5V, Unless Otherwise Noted. (9) CLK TCLR1X (7) TRIVCH RDY1.2 (12) TA1VR1V ...
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Timing Waveforms (Continued) CLK RDY1, 2 (12) TA1VRIV AEN1, 2 ASYNC READY FIGURE 9. WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES) EFI CLK CLK50 PCLK S0 (18) TSVCH S1 (18) TSVCH S2/STOP RES START FIGURE 10. CLOCK STOP (F/C HIGH ...
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Timing Waveforms (Continued) EFI CLK CLK50 PCLK S0 S1 S2/STOP RES START (21) TSHSL START (39) TOST X1 CRYSTAL OSCILLATOR STARTUP TIME CLK CLK50 PCLK NOTE: Start up count begins when the crystal oscillator reaches a suitable threshold level. 82C85 ...
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Timing Waveforms (Continued) RES (17) TI1HCL CLK RESET FIGURE 13. RESET TIMING (CLK RUNNING WITH F/C LOW-OSC MODE) (CLK RUNNING-OR STOPPED WITH F/C HIGH EFI MODE) RES (21) TSHSL CLK RESET OSCILLATOR STARTUP 8192 TIME CYCLES X1 (39) TOST FIGURE ...
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Timing Waveforms (Continued) EFI OR OSC PCLK SLO/FST CLK CLK50 NOTE: See Fast to Slow Clock Mode Transition for Detailed Timing; See Slow to Fast Clock Mode Transition for Detailed Timing OR OSC CYCLES EFI OR OSC PCLK TSFPC (22) ...
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Timing Waveforms (Continued) EFI OR OSC PCLK SLO/FST CLK CLK50 FIGURE 17. SLOW TO FAST CLOCK MODE TRANSITION NOTE: IF TSFPC is not met on one edge of PLCK. SLO/FST will be recognized on the next edge of PLCK. 82C85 ...
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Test Load Circuits PASSIVE LOAD V R FROM OUTPUT UNDER TEST CL SEE NOTE 360 2.25 for CLK and CLK50 outputs R = 470 2.87 for all other outputs (Except X2) ...
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Burn-In Circuits R 1 GND GND GND GND ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...