KU80960CF-33 Intel Corporation, KU80960CF-33 Datasheet
KU80960CF-33
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KU80960CF-33 Summary of contents
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... High Bandwidth On-Chip Data RAM — 1 Kbyte On-Chip Data RAM — Sustains 128 bits per Clock Access Selectable Big or Little Endian Byte Ordering © INTEL CORPORATION, 1996 Four On-Chip DMA Channels — 71 Mbytes/s Fly-by Transfers — 40 Mbytes/s Two-Cycle Transfers — Data Chaining — ...
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... Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-764 or call 1-800-548-4725 ...
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HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR 1.0 PURPOSE .................................................................................................................................................. 1 2.0 80960CF OVERVIEW ................................................................................................................................ 1 2.1 The 80960C-Series Core .................................................................................................................... 3 2.2 Pipelined, Burst Bus ........................................................................................................................... 3 2.3 Instruction Set Summary .................................................................................................................... 3 2.4 Flexible DMA Controller ...
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CONTENTS FIGURES Figure 1. 80960CF Block Diagram ............................................................................................................ 2 Figure 2. 80960CF PGA Pinout—View from Top (Pins Facing Down) .................................................... 12 Figure 3. 80960CF PGA Pinout — View from Bottom (Pins Facing Up) ................................................. 13 Figure 4. 80960CF PQFP Pinout—Top ...
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Figure 40. Using External READY ............................................................................................................ 63 Figure 41. Terminating a Burst with BTERM ............................................................................................. 64 Figure 42. BOFF Functional Timing .......................................................................................................... 65 Figure 43. HOLD Functional Timing .......................................................................................................... 66 Figure 44. DREQ and DACK Functional Timing ....................................................................................... 67 Figure ...
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PURPOSE This document provides electrical characteristics of ® Intel’s i960 CF embedded microprocessor. For functional descriptions consult the i960 processor User’s Manual (270710). To obtain data sheet updates and errata, contact Intel at any of the following numbers. Intel’s ...
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Interrupt Port Programmable Interrupt Controller Multiply/Divide Unit Execution Unit The 80960CF, object code compatible with the 32-bit 80960 core Architecture, employs Special Function Register extensions to control on-chip peripherals and instruction set extensions to shift 64-bit ...
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The processor also integrates four complete data- chaining DMA channels and a high-speed interrupt controller on-chip. DMA channels perform single- cycle or two-cycle transfers, data packing and unpacking and data chaining. Block transfers — in addition to source or destination ...
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Priority Interrupt Controller A programmable-priority interrupt manages up to 248 external sources through the 8- bit external interrupt port. The Interrupt Unit also handles the four internal sources from the DMA controller and a single ...
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PACKAGE INFORMATION 3.1 Package Introduction This section describes the pins, pinouts and thermal characteristics for the 80960CF in the 168-pin Ceramic Pin Grid Array (PGA) package; the 80960CF-33, -25, -16 devices are also available in the 196-pin Plastic Quad ...
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Table 2. 80960CF Pin Description — External Bus Signals (Sheet Name Type A31:2 O ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most significant S bit least ...
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Table 2. 80960CF Pin Description — External Bus Signals (Sheet Name Type BTERM I BURST TERMINATE is an input which breaks up a burst access and causes another S(L) address cycle to occur. The BTERM signal works ...
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Table 2. 80960CF Pin Description — External Bus Signals (Sheet Name Type HOLDA O HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relin- S quished control of the external bus. ...
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Table 3. 80960CF Pin Description — Processor Control Signals (Sheet Name Type RESET I RESET causes the chip to reset. When RESET is asserted, all external signals return A(L) to the reset state. When RESET is deasserted, ...
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Table 3. 80960CF Pin Description — Processor Control Signals (Sheet Name Type CLKIN I CLOCK INPUT is an input for the external clock needed to run the processor. The A(E) external clock is ...
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Table 4. 80960CF Pin Description — DMA and Interrupt Unit Control Signals Name Type DREQ3:0 I DMA REQUEST is used to request a DMA transfer. Each of the four signals A(L) requests a transfer on a single channel. DREQ0 requests ...
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Mechanical Data 3.3.1 80960CF PGA PINOUT Figure 2 depicts the complete 80960CF PGA pinout as viewed from the top side of the component (i.e., pins facing down). Figure 3 shows the complete S R ...
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BOFF FAIL STEST ONCE DREQ0 NC 6 DREQ1 DREQ2 ...
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Table 5. 80960CF PGA Pinout — In Signal Order Address Bus Data Bus Signal Pin Signal Pin A31 S15 D31 R3 A30 Q13 D30 Q5 A29 R14 D29 S2 A28 Q14 D28 Q4 A27 S16 D27 ...
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Table 6. 80960CF PGA Pinout — In Pin Order Pin Signal Pin Signal FAIL ONCE DREQ1 DREQ3 ...
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PQFP Pinout (80960CF-33, -25, -16 Only) Tables 7 and 8 list the 80960CF pin names with package location. Figure 4 shows the 80960CF PQFP pinout as viewed from the top side. See Section 4.0, ...
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Table 7. 80960CF PQFP Pinout — In Signal Order (80960CF-33, -25, -16 Only) Address Bus Data Bus Signal Pin Signal A31 153 D31 186 A30 152 D30 187 A29 151 D29 188 A28 145 D28 189 A27 144 D27 191 ...
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Table 8. 80960CF PQFP Pinout — In Pin Order (80960CF-33, -25, -16 Only) Pin Signal Pin Signal D23 D22 ...
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Figure 4. 80960CF PQFP Pinout—Top View (80960CF-33, -25, -16 Only) 3.4 Package Thermal Specifications The 80960CF is specified for operation when T (case temperature) is within the range of 0°C–100°C for 33, 25, and 16 MHz ...
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Measure PGA temperature at center of top surface 168 - Pin PGA Figure 5. Measuring 80960CF PGA and PQFP Case Temperature Table 9. Maximum T f PCLK (MHz) T with Heatsink ...
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Table 10. 80960CF PGA Package Thermal Characteristics Thermal Resistance — °C/Watt Parameter 0 200 (0) (1.01) Junction-to-Case 1.5 1.5 (Case measured as shown in Figure 5) Case-to-Ambient 17 14 (No Heatsink) Case-to-Ambient 13 9 (With Heatsink)* NOTES: 1. This table ...
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Stepping Register Information Upon reset, register g0 contains die stepping infor- mation (Figure 6). The most significant byte contains ASCII 0; the upper middle byte contains an ASCII C; the lower middle byte contains an ...
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ELECTRICAL SPECIFICATIONS 4.1 Absolute Maximum Ratings Parameter Maximum Rating Storage Temperature................................ –65°C to +150°C Case Temperature Under Bias ..................–65°C to +110°C Supply Voltage wrt. V ............................–0 6 Voltage on Other Pins wrt. V ......... ...
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Recommended Connections Power and ground connections must be made to multiple V and V (GND) pins. Every 80960CF based circuit board should include power (V ground (V ) planes for power distribution. Every ...
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Table 14. DC Characteristics (Sheet (80960CF-40, 33, -25, -16 under the conditions described in Section 4.2, Operating Conditions.) Symbol Parameter Input Leakage Current for each pin except : I LI1 BTERM, ONCE, DREQ3:0, STEST, EOP3:0/TC3:0, NMI, XINT7:0, ...
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AC Specifications Table 15. 80960CF AC Characteristics (40 MHz) (Sheet (80960CF-40 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) Symbol Parameter Input Clock (1,9) T CLKIN Frequency ...
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Table 15. 80960CF AC Characteristics (40 MHz) (Sheet (80960CF-40 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) Symbol Parameter T Output Valid Delay, Output Hold OH1 ...
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Table 15. 80960CF AC Characteristics (40 MHz) (Sheet (80960CF-40 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) Symbol Parameter Relative Output Timings (1,2,3,8) T A31:2 Valid to ADS ...
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Table 16. 80960CF AC Characteristics (33 MHz) (Sheet (80960CF-33 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) Symbol Parameter Input Clock (1,9) T CLKIN Frequency F T CLKIN Period C T CLKIN ...
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Table 16. 80960CF AC Characteristics (33 MHz) (Sheet (80960CF-33 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) Symbol Parameter Synchronous Outputs (8) T Output Valid Delay, Output Hold ...
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Table 16. 80960CF AC Characteristics (33 MHz) (Sheet (80960CF-33 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) Symbol Parameter T Output Data Valid to WAIT Rising DVNH T WAIT Falling to WAIT ...
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Table 17. 80960CF AC Characteristics (25 MHz) (Sheet (80960CF-25 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) Symbol Parameter Input Clock (1,9) T CLKIN Frequency F T CLKIN ...
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Table 17. 80960CF AC Characteristics (25 MHz) (Sheet (80960CF-25 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) Symbol Parameter Synchronous Inputs (1,9,10) T Input Setup IS T IS1 T IS2 T IS3 ...
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Table 18. 80960CF AC Characteristics (16 MHz) (Sheet 80960CF-16 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) ( Symbol Parameter Input Clock (1,9) T CLKIN Frequency F T ...
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Table 18. 80960CF AC Characteristics (16 MHz) (Sheet 80960CF-16 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) ( Symbol Parameter Synchronous Inputs (1,9,10) T Input Setup IS T IS1 T IS2 T ...
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Table 18. 80960CF AC Characteristics (16 MHz) (Sheet 80960CF-16 only, per the conditions in 4.2 Operating Conditions and 4.5.1 AC TEST CONDITIONS.) ( Symbol Parameter T XINT7:0, NMI Input Hold IH7 T RESET ...
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AC TIMING WAVEFORMS 1.5 V CLKIN PCLK2:1 Figure 8. Input and Output Clocks Waveform T CR PRELIMINARY Output Pin for all signals L F_CX008A Figure 7. AC Test Load T CP 1.5 V ...
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PCLK2:1 Outputs Outputs NOTES OUTPUT DELAY - Maximum output delay is referred to as Output Valid Delay ( output delay is referred to as Output Hold ( ...
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PCLK2:1 NMI, XINT7:0 Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform PCLK2:1 Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA T Min 1.5 V HOLD HOLDA NOTES OUTPUT DELAY ...
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PCLK2:1 Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA BOFF 1.5 V Figure 14. Bus Backoff (BOFF) Timings PCLK2:1 1.5 V ADS A31:2, BE3:0, W/R, LOCK, SUP, D/C, DMA D31:0 ...
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DERATING CURVES nom + 10 nom + 5 nom 50 C Figure 16. Output Delay or Hold vs. Load Capacitance 0 2 (pF) 50 100 L a) All outputs except: ...
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under test conditions CC CC Figure 18. I vs. Frequency and Temperature—80960CF-33, -25, -16 CC 1100 (MHz) 0 PCLK Figure 19 5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE ...
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Table 19. Reset Conditions State During Reset Pins (HOLDA inactive) A31:2 Floating D31:0 Floating BE3:0 Driven high (Inactive) W/R Driven low (Read) Driven high (Inactive) ADS WAIT Driven high (Inactive) BLAST Driven low (Active) DT/R Driven low (Receive) DEN Driven ...
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BUS WAVEFORMS 44 Figure 20. Cold Reset Waveform PRELIMINARY ...
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Figure 21. Warm Reset Waveform PRELIMINARY 80960CF-40, -33, -25, -16 45 ...
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Figure 22. Entering the ONCE State PRELIMINARY ...
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V CLKIN T RESET 1.5 V PCLK2:1 (Case 1) Max Min PCLK2:1 (Case 2) Note: Case 1 and Case 2 show two possible polarities of PCLK2:1 Figure 23. Clock Synchronization in the 2-x Clock Mode 2x CLK 1.5 V ...
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Byte Function Order Bit 31- Value 0.. PCLK ADS A31:4, SUP , DMA, D/C, BE3:0, LOCK BLAST DEN A3:2 WAIT D31:0 Figure ...
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Byte Bus Function Order Width Bit 31- 20- Value 0.. PCLK ADS A31:2, BE3:0 W/R BLAST DT/R DEN DMA, D/C, SUP, LOCK WAIT D31:0 Figure 26. Non-Burst, Non-Pipelined Read Request ...
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Byte Function Order Bit 31- Value 0.. PCLK ADS A31:2, BE3:0 W/R BLAST DT/R DEN SUP, DMA, D/C, LOCK WAIT D31:0 Figure 27. Non-Burst, Non-Pipelined Write Request With ...
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Byte Function Order Bit 31- Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK BLAST DEN A3:2 WAIT D31:0 Figure 28. Burst, Non-Pipelined Read Request ...
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Byte Function Order Bit 22 21 31- Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0 Figure 29. Burst, Non-Pipelined Read ...
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Byte Bus Function Order Width Bit 22 21 20-19 31-23 32-bit Value 0.. PCLK ADS A31:4, SUP , DMA, D/C, BE3:0, LOCK BLAST DEN A3:2 WAIT D31:0 ...
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Byte Function Order Bit 22 21 31- Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0 Figure 31. Burst, Non-Pipelined Write ...
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Byte Bus Function Order Width Bit 31- 20-19 0 16-bit 0 X Value 0.. PCLK ADS SUP, DMA, D/C, LOCK, A31:4, BE3/BHE, BE0/BLE W/R BLAST DT/R DEN A3:2 BE1/A1 WAIT D31:0 Figure 32. ...
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Byte Function Order Bit 31- Value 0.. PCLK ADS SUP, DMA, D/C, LOCK, A31:4 W/R BLAST DT/R DEN A3:2 BE1/A1, BE0/A0 WAIT D31:0 Figure 33. Burst, Non-Pipelined Read ...
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Byte Function Order Width Bit 31- 20- Value 0.. PCLK ADS A31:4, SUP, Valid DMA, D/C, LOCK W/R A3:2 Valid BE3:0 D31:0 WAIT BLAST DT/R DEN Non-pipelined request concludes pipelined reads begin. ...
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Byte Function Order Bit 22 21 31- Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, LOCK W/R A3:2 BE3:0 D31:0 WAIT BLAST DT/R DEN Non-pipelined request concludes pipelined reads begin. ...
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Byte Bus Function Order Width 22 21 20-19 Bit 31- 32-bit X Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R A3:2 00 D31:0 WAIT BLAST DT/R DEN Figure 36. Burst, Pipelined ...
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Byte Function Order Bit 31- Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R 00 A3:2 D31:0 WAIT BLAST DT/R DEN Non-pipelined request concludes, ...
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Byte Bus Function Order Width Bit 22 21 20-19 31- 16-bit Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, BE0/BLE, BE3/BHE, LOCK W/R A3:2 A3 BE1 /A1 ...
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Byte Function Order Width Bit 22 21 20-19 31- Value 0.. PCLK ADS A31:4, SUP, DMA, D/C, LOCK W/R A3:2 BE1/A1, A1 BE0/A0 D31:0 WAIT BLAST ...
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Quad-Word Read Request RAD RDD Ready Enabled PCLK ADS A31:4, SUP, DMA, INST, Valid D/C, BE3:0, LOCK W/R BLAST DT/R DEN READY BTERM A3:2 00 WAIT D0 D31:0 Figure 40. Using External READY ...
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PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0, LOCK W/R BLAST DT/R DEN READY BTERM A3:2 00 WAIT D31:0 Note: READY adds memory access time to data transfers, whether or not the bus access is a ...
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ADS BLAST READY BOFF SUSPEND REQUEST A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R D31:0, (WRITES) Begin Request BOFF may not be asserted Note: READY/BTERM must be enabled; N Figure 42. BOFF Functional Timing PRELIMINARY 80960CF-40, -33, -25, -16 Regenerate ...
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Word Read Request PCLK2:1 ADS A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R BLAST HOLD HOLDA 66 Word Read Hold State N = RAD XDA Valid Figure 43. HOLD Functional Timing Request N =0, ...
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PCLK2:1 ADS BLAST ! ( READY & !WAIT & ) (see Note) DACKx (All Modes) DREQx (Case 1) DREQx (Case 2) Note: 1. Case 1: DREQ must deassert before DACK deasserts. This applies to all Fly-By modes: source synchronized packing ...
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PCLK2:1 DREQ ADS DACK TC Note: Terminal Count becomes active during the last bus request of a buffer transfer. If the last LOAD/STORE bus request is executed as multiple bus accesses, the TC will be active ...
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Byte Offset Word Offset 0 1 Short Request (Aligned) Byte, Byte Requests Short-Word Load/Store Short Request (Aligned) Byte, Byte Requests Word Request (Aligned) Byte, Short, Byte, Requests Word Load/Store Double-Word Load/Store Figure 48. A Summary of Aligned and ...
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Byte Offset 0 1 Word Offset Triple-Word Load/Store Quad-Word Load/Store Figure 49. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued One Three-Word Request ...
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Write Request N = WAD XDA Ready Disabled PCLK ADS A31:4, SUP, Valid DMA, INST, D/C, BE3:0 LOCK Valid W/R BLAST DT/R DEN A3:2 Valid WAIT D31:0 Out READY, BTERM 7.0 REVISION HISTORY This is a new ...