ISL3873AIK-TK Intersil Corporation, ISL3873AIK-TK Datasheet
ISL3873AIK-TK
Related parts for ISL3873AIK-TK
ISL3873AIK-TK Summary of contents
Page 1
... NUMBER RANGE ( C) PACKAGE ISL3873AIK - 192 BGA ISL3873AIK-TK - Tape and Reel 1000 Units /Reel 1 September 2001 Features • PCMCIA Host Interface and compatibility with USB V1.1. • New Start Up Modes Allow the PCMCIA Card Information Structure to be Initialized From a Serial EEPROM. This ...
Page 2
Simplified Block Diagram HOST COMPUTER DATA ADDRESS CONTROL PC CARD HOST INTERFACE MICRO- PROGRAMMED MAC ENGINE WEP ENGINE ON-CHIP ROM MEMORY CONTROLLER ON-CHIP RAM MEDIUM ACCESS ADDRESS DATA SELECT EXTERNAL SRAM AND FLASH MEMORY 2 ISL3873A USB ISL3873A USB HOST ...
Page 3
ISL3873A Signal Descriptions PIN NAME PIN I/O TYPE HA0-9 5V tol, CMOS, Input, 50K Pull Down HCE1- 5V tol, CMOS, Input, 50K Pull Up HCE2- 5V tol, CMOS, Input, 50K Pull Up HD0-15 5V tol, BiDir, 2mA, 50K Pull Down ...
Page 4
PIN NAME PIN I/O TYPE PJ4 CMOS BiDir, 2mA PJ5 CMOS BiDir, 2mA, 50K Pull Up PJ6 CMOS BiDir, 2mA PJ7 CMOS BiDir, 2mA, 50K Pull Up PK0 CMOS BiDir, 2mA, ST, 50K Pull Down PK1 CMOS BiDir, 2mA, 50K ...
Page 5
PIN NAME PIN I/O TYPE ANTSEL O ANTSEL O TestMode I/O CompCap1 I CompCap2 I CompRes1 I CompRes2 I DBG(0-4) I/O PIN NAME PIN I/O TYPE V Power DDA V Power DD SUPPLY5V Power V Ground SSA V Ground sub ...
Page 6
PIN NUMBER SIGNAL NAME PIN NUMBER MA9 B4 MA12 MA18 B7 DBG1 B8 HD12 B9 HCE1 B10 V DD B11 HIORD B12 HA8 B13 HWE B14 HA4 B15 NC B16 DBG4 C1 MA6 ...
Page 7
Absolute Maximum Ratings Supply Voltage 3.6V ...
Page 8
AC Electrical Specifications (Continued) PARAMETER SYNTHCLK(PK1) Width Hi SYNTHCLK(PK1) Width Lo SERIAL PORT SYNTHCLK(PK1) Clock Period Low Width Delay from Clock Falling Edge to SPCSx, SPAS, SPREAD, SYNTHDATA(PK2) Outputs Setup Time of SYTHNDATA(PK2) Read to SYTHNCLK(PK1) Falling Edge Hold Time ...
Page 9
Waveforms ADDRESS MA(17..1) RAMCS_ MOE_ t S2 MD(15..0) ADDRESS MA(17..1) RAMCS_ MWE_ MD(15..0) SYNTHCLK SYNLE SPCSPWR t D1 SYNTHDATA 9 ISL3873A FIGURE 1. EXTERNAL MEMORY READ TIMING ...
Page 10
Waveforms (Continued) HA[15:0] HREG- HCE( HIORD- t SUA HINPACK- HWAIT- HD[15:0] HA[15:0] HREGN- HCE ( HIOWR- HWAIT- t SUIOWR HD[15: ISL3873A t t SUREG HREG I t SUCE HCE t WIORD t DIORD t ...
Page 11
ISL3873A MAC System Overview ISL3873A MD0..15 MA1..17 NVCS_ MOE_ MWEL_ MA0/MWEH_ RAMCS_ FIGURE 6. 8-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873A ISL3873A MA1..17 MD0..15 NVCS- MA0/MWEH- MLBE- RAMCS- MOE- MWEL- FIGURE 7. 16-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873A 11 ISL3873A SRAM ...
Page 12
LARGE SERIAL EEPROM MISO (PJ2) SD (PJ1) ISL3873A SCLK (PJ0) CS# (TCLKIN) PULLUP External Memory Interface The ISL3873A provides separate external chip selects for code space and data storage space. Code space is accessible as data space through an overlay ...
Page 13
For 8-bit spaces, the ISL3873A dynamically configures pin MUBE-/MA0/MWEH- cycle-by-cycle as the address LSB. MWEL-/MWE- is the only write control, and MOE- is the read output enable. For 16-bit spaces constructed from 8-bit memories, the ISL3873A dynamically configures pin MUBE-/MA0/MWEH- ...
Page 14
Read to Attribute Space and Memory Mapped Registers • WAIT will assert until the memory arbitration and access have completed. Buffer Access Paths, BAP0 and BAP1 • An internal Pre-Read cycle to memory is initiated by a host Buffer Read ...
Page 15
FID ALLOCATE/ DEALLOCATE REQUEST OFFSET CENTER HOST BUS DATA PORT PRE-READ/ POST-WRITE FIGURE 9. BLOCK DIAGRAM OF A BUFFER ACCESS PATH USB Port The USB interface implemented in the ISL3873A Is compatible with the Universal Serial Bus Specification Revision 1.1. ...
Page 16
PE1 PE2 t PA_PE D1 TR_SW TR_SW_BAR TABLE 1. TRANSMIT CONTROL TIMING SPECIFICATIONS PARAMETER SYMBOL DELAY PE2 to PA_PE t 0.1 D1 TPE2 to TR Switch t 1 Switch to PE2 PA_PE to PE2 t ...
Page 17
When using a 48MHz CLKIN typical for 802.11 or 802.11b controllers with a USB host interface, common divisors are 4 (12MHz (8MHz) The MCLK prescaler is set to divide hardware reset to ...
Page 18
Baseband Processor The Baseband Processor operation is controlled by the ISL3873A firmware. Detailed information on programming the Baseband Processor can be obtain by contacting the factory. BBP Packet Reception The receive demodulator scrutinizes I and Q for packet activity. When ...
Page 19
DQPSK, or CCK. The preamble is used by the receiver to achieve initial Pseudo Noise (PN) synchronization while the header includes the necessary data fields of the communications protocol to establish the physical layer link. The transmitter generates the synchronization ...
Page 20
DSSS BPSK 1Mbps BARKER DATA 1 BIT ENCODED TO ONE OF 2 CODE WORDS (TRUE-INVERSE) I OUT Q OUT 11 CHIPS CHIP 11 MC/S RATE SYMBOL 1 MS/S RATE I vs. Q PREAMBLE (SYNC) Start FRAME DELIMITER 128/56 BITS ...
Page 21
Defines the short preamble length minus the SFD in symbols. The 802.11 protocol requires a setting of 56d = 38h for the optional short preamble Defines the long preamble length minus the SFD in ...
Page 22
The terms: ϕ1, ϕ2, ϕ3, and ϕ4 are defined below for 5.5Mbps and 11Mbps. This formula creates 8 complex chips (LSB to MSB) that are transmitted LSB first. The coding is a form of the generalized Hadamard transform encoding where ...
Page 23
MAC in executing algorithms that can adapt to the environment. These algorithms can increase network throughput by minimizing collisions and reducing transmissions liable to errors. There are three measures that can be used in the ...
Page 24
RX_RF_AGC Pad Operation 30dB Pad Engaging (RF Chip Low Gain): If the AGC is not locked onto a packet, a '1' on the ifCompDet input will engage in the 30dB attenuation pad. This causes the AGC to go out of ...
Page 25
TX POWER RAMP 2 20 SYMBOLS AGC SETTLE AND LOCK AND INITIAL DETECTION V (ANALOG) DDA I REF V REF 6-BIT TX_AGC_IN ADC 6-BIT TX_IF_AGC DAC ANTSEL ANTSEL TX_PE FIGURE 17. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION Meanwhile signal quality and ...
Page 26
Channel Matched Filter (CMF) Description The receive section shown in Figure 19 operates on the RAKE receiver principle which maximizes the SNR of the signal by combining the energy of multipath signal components. The RAKE receiver is implemented with a ...
Page 27
SAMPLES AT 2X CHIP T0 CORRELATOR OUTPUT IS THE RESULT OF CORRELATING THE PSEUDO NOISE(PN) SEQUENCE WITH THE RECEIVED SIGNAL Data Demodulation in the CCK Modes In this mode, the demodulator uses Complementary Code Keying (CCK) modulation for the two ...
Page 28
V (ANALOG) DDA RX_IF_DET RX_IF_AGC AGC CONTROL 6-BIT RX_RF_AGC DAC DIVERSITY ANT SEL CONTROL 6-BIT RXI A/D 6 6-BIT RXQ A/D 6 COHERENT TIMING INTEGRATOR ANTENNA ANTSEL SWITCH ANTSEL CONTROL TIMING GENERATOR MCLK RESET RX_PE FIGURE 19. DSSS BASEBAND PROCESSOR, ...
Page 29
Demodulator Performance This section indicates the typical performance measures for a radio design. The performance data below should be used as a guide. In general, the actual performance depends on the application, interference environment, RF/IF implementation and radio component selection. ...
Page 30
RSSI Performance The RSSI value is reported on CR62 in hex and is linear with signal level in dB. Figure 22 shows the RSSI curve measured on a whole evaluation radio. This takes into account the full gain adjust range ...
Page 31
Control Registers The following tables describe the function of each control register along with the associated bits in each control register. CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE Bit 7:4 Part Code 3 = HFA3863 series Bit 3:0 Version ...
Page 32
CONFIGURATION REGISTER 5 ADDRESS (0Ah) R/W TX SIGNAL FIELD Bits 7:5 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 4 TX/RX filter / CMF weight select US. 1 ...
Page 33
CONFIGURATION REGISTER 10 ADDRESS (14h) R/W RX CONFIGURE Bit 7 AGC freeze during packet Disable (do not disable unless MAC can handle baseband processor aborting during MPDU reception Enable. Bit 6 CIR estimate/ Dot product clock ...
Page 34
CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 (Continued) Bit 3 Q DAC clock enable disable. Bit 2 RF A/D clock enable disable. Bit 1 I A/D clock ...
Page 35
CONFIGURATION REGISTER 14 ADDRESS (1Ch) R/W A/D TEST MODES 3 (Continued) Bit 3 Enable test bus into RX and TX DAC (if below bit normal enable. Bit 2 Enable RF A/D into RX ...
Page 36
CONFIGURATION REGISTER 23 ADDRESS (2Eh) R/W AGC TABLE DATA Bits 7 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bits 6:0 AGC look up table data, unsigned. CONFIGURATION REGISTER 24 ADDRESS ...
Page 37
CONFIGURATION REGISTER ADDRESS 30 (3Ch) R/W CARRIER SENSE 2 SCALE FACTOR Bits 7:6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 5:0 Carrier Sense 2 (CS2) scale factor (0-7.875 range) ...
Page 38
CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TEST MODES 2 (Continued) Bit 2 Internal digital loop back mode (SDI pin becomes LOCK input to acquisition block normal chip operation loop back disabled loop back enabled, A/D and ...
Page 39
CONFIGURATION REGISTER ADDRESS 41 (52h) R/W PREAMBLE/HEADER LEAD COEFFICIENT Bit 7:6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 5:0 Preamble Lead Coefficient (0-4 range) (000000 - 100000). CONFIGURATION REGISTER ...
Page 40
CONFIGURATION REGISTER ADDRESS 51 (66h) R SIGNAL QUALITY MEASURE Bit 7:0 a: NOISEfloorAntA [7:0] unsigned, range 0-255. b: measures signal quality based on the SNR in the carrier tracking loop. CONFIGURATION REGISTER ADDRESS 52 (68h) R RECEIVED SIGNAL FIELD Bit ...
Page 41
Bit 7:0 a&b: 8-bit value of Packet RSSI, unsigned, range 0 to 255 dB. CONFIGURATION REGISTER ADDRESS 63 (80h) R RECEIVE STATUS Bit 7:6 a&b: signal field value (HRfieldmatch/QPSKwd_OK 5. ...
Page 42
... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. ...