HDMP-1512 Agilent Technologies, Inc., HDMP-1512 Datasheet
HDMP-1512
Specifications of HDMP-1512
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HDMP-1512 Summary of contents
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... Channel • Work Station/Server I/O Channel • High Speed Peripheral Interface Description The HDMP-1512 transmitter and the HDMP-1514 receiver are bipolar integrated circuits, separately packaged pin M- Quad packages. They are used to build a high speed Fibre Channel link for point to point data com- munications ...
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... DATA BYTE 0 TTL INTERFACE Tx [00:09] INPUT LATCH DATA BYTE 1 Tx [10:19] 10 TBC Figure 2. HDMP-1512 (Tx) Block Diagram. Transmitter Operation The block diagram of the HDMP- 1512 transmitter is shown in Figure 2. The basic functions of the transmitter chip are the TTL Interface and Input Latch, Frame Multiplexing, Input/Output ...
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... Fibre Channel character, K28.5 instead. The 8B/10B coding scheme, adopted by Fibre Channel, con- verts 8 bit data words into 10 bit representations of the actual data. Of all the possible combina- HDMP-1512 Input Output Select Table Mode TS1 TS2 EWRAP ...
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... Figure 3. Laser Driver Block Diagram and External Circuitry. described in more detail in the laser driver operation section below. Transmitter Laser Driver Operation The block diagram of the HDMP- 1512, Tx, laser driver circuitry is shown in Figure 3. The laser driver is enabled by setting -LZON (pin 30) low and LZPWRON (pin 36) high. The ...
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... INPUT SELECT -EQEN ± LIN V _HS CC SUPPLY SUPERVISOR Figure 5. HDMP-1514 (Receiver) Block Diagram. 660 Receiver Operation The block diagram of the HDMP- 1514 receiver is shown in Figure 5. The functions included on the receiver are a coaxial cable equalizer, two independent loss of light (LOL) detectors, an input ...
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Setting pin #32 high disables the equalizer. Setting pin # 32 low enables the equalizer. The typical performance of the input equalizer is shown in the (frequency response) plot of Figure 7. The ...
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EWRAP The table above llustrates these various settings. Normally, the recovered serial clock is used by the clock gener- ator to generate the various internal clocks the receiver uses ...
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... ESD sensitive and standard procedures for static sensitive devices should be used in the handling and assembly of the HDMP-1512 and the HDMP-1514. The packing materials used for shipment of these devices was selected to provide ESD protection and to prevent mechanical damage ...
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... HDMP-1512 (Tx), HDMP-1514 (Rx) Transmitter & Receiver Byte Rate Clock Requirements + 4 5 Symbol f Nominal Frequency F Frequency Tolerance (For Fibre Channel Compliance) tol Symm Symmetry (Duty Cycle) HDMP-1512 (Tx), HDMP-1514 (Rx) AC Electrical Specifications + 4 5.5 V, Unless Otherwise Specified ...
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... HDMP-1512 (Tx), HDMP-1514 (Rx) DC Electrical Specifications + 4 5 Symbol V TTL Input High Voltage Level, Guaranteed high signal for IH,TTL all inputs 100 TTL Input Low Voltage Level, Guaranteed low signal for all IL,TTL inputs -1mA IL V TTL Output High Voltage Level, I ...
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... The Receiver Latency is defined as the delay time from receiving the first serial bit of a parallel data word (defined by the rising edge of the first bit received at pins DI), and when that word is first clocked out at RX[00:19] (as defined by the falling edge of RBC0 or RBC1, following time HDMP-1512 (Tx), HDMP-1514 (Rx) Thermal Characteristics + Symbol P ...
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O_TTL V _TTL CC V _LOG CC 800 72 ESD ESD GND_LOG GND_TTL Figure 9. O-TTL and I-TTL Simplified Circuit Schematic. O-BLL V _HS CC V _LOG ESD ESD ESD ESD GND_HS GND_LOG Figure ...
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... GND_LOG 70 EWRAP 71 V _LOG 72 CC TBC 73 GND_LOG 74 TS2 75 TS1 CAP0A 79 CAP0B Figure 11. HDMP-1512 (Tx) Package Layout, Top View. 668 Name Pin Name LZDC 41 VCC_TTL LZMDF 42 VCC_TTL VCC_LZ 43 TX[00] VCC_LZ 44 TX[01] GND_LZ 45 TX[02] GND_LZ 46 TX[03] LZTC 47 TX[04] LZBTP 48 TX[05] FAULT 49 TX[06] -LZON 50 ...
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... HDMP-1512 (Tx), Signal Definitions Symbol Signal Name CAP0[A:B] Loop Filter Capacitor Pins [79,80] CAP1[A:B] Loop Filter Capacitor Pins [1,2] -COMGEN Comma Generate Pin [32] -ECLKSEL External Clock Select Pin [69] EWRAP Enable Wrap Pin [71] FAULT Laser Fault Indicator Pin [29] GND_A Analog Ground Pins [3,4] GND_LOG Logic Ground ...
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... HDMP-1512 (Tx), Signal Definitions (cont’d.) Symbol Signal Name LZPWRON Laser Power On Pin [36] LZTC Laser Timing Cap Pin [27] PPSEL Ping-Pong Select Pin [34] SI Laser External Serial Input Pins [11,12] SO Cable Serial Data Output Pins [5,6] SPDSEL Serial Speed Select Pin [67] TBC Transmit Byte Clock ...
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... HDMP-1512 (Tx), Signal Definitions (cont’d.) Symbol Signal Name VCC_LZAC Laser Power Supply Pin [17] VCC_LZBG Laser Power Supply Pins [15] VCC_TTL TTL Power Supply Pins [41,42,63,64] NC Pin [38 GND_TTL 65 GND_TTL 66 RBC[ _LOG ...
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... VCC_HS2 35 16 -LIN 36 17 +LIN 37 18 VCC_HS2 +DI 40 HDMP-1514 (Rx), Signal Definitions Symbol Signal Name CAP0[A:B] Loop Filter Capacitor Pins [79,80] CAP1[A:B] Loop Filter Capacitor Pins [1,2] CLKIN Receive Reference (TCLK) Clock Pin [7] COM_DET Comma Detect Pin [75] DI Serial Data Inputs ...
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... HDMP-1514 (Rx), Signal Definitions (cont’d.) Symbol Signal Name DR_REF Receiver Reference Pin [21] EN_CDET Enable Comma Detect Pin [38] -EQEN Equalizer Enable Input Input Pin [32] EWRAP Enable Wrap Pin [71] GND_A Analog Ground Pins [3,4] GND_HS High Speed Ground Pins [14,25,26] GND_LOG Logic Ground Pins[31,35,70,74] GND_TTL ...
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... HDMP-1514 (Rx), Signal Definitions (cont’d.) Symbol Signal Name PPSEL Ping-Pong Select Pin [76] PS_CT Power Supply Timing Cap Pin [22] RBC[0:1] Receive Byte Clocks Pin [67, 69] RX[00:19] Data Outputs Pins [43, 62] SPDSEL Serial Speed Select Pin [71] -TCLKSEL Test Clock Select Pin [5] VCC_A Analog Supply ...
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... TOP VIEW + 0.16 13.792 - 0.04 + 0.008 ( ) 0.543 - 0.002 17.20 ± 0.10 (0.677 ± 0.004) ALL DIMENSIONS ARE IN MILLIMETERS (INCHES). Figure 13. HDMP-1512 and HDMP-1514 Package Outline. M-Quad 80 Package Specifications Item Package Material Lead Finish Material Lead Finish Thickness Lead Coplanarity 23.20 ± 0.10 (0.913 ± 0.004) + 0.18 19.786 - 0.08 + 0.008 ...
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... TBC Tx[00:19] DATA Figure 14. HDMP-1512 (Transmitter) Timing Diagram, with PPSEL = 0. COM_DET Rx[00:19] RBCO Figure 15. HDMP-1514 (Receiver) Timing Diagram, with PPSEL = 0. 676 ts th DATA DATA DATA K28.5 DATA 18.8 ns DATA DATA ...
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... TBC Tx[00:09] DATA Tx[10:19] DATA Figure 16. HDMP-1512 (Transmitter) Timing Diagram In Ping-Pong Mode, PPSEL = 1. Rx[10:19] RBC1 COM_DET Rx[00:09] K28.5 ts' th' RBC0 Figure 17. HDMP-1514 (Receiver) Timing Diagram in Ping-Pong Mode, with PPSEL = ...
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... Figure 18. Typical Transmitter Pin Terminations for Applications Requiring High Speed Serial Copper Drivers ( So). Laser Driver Outputs are Disabled. For 1062.5 MBd Operation Only, SPDSEL (pin 67) Set High, Non Ping-Pong Mode (PPSEL = 0). 678 HDMP-1512 TOP VIEW 0.1 µ ...
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... Figure 19. Typical Transmitter Pin Terminations for Applications Using the On-Chip Laser Driver. For Details of the Laser Driver Connections, Indicated by “*,” see Figure 3 on page 4. For 1062.5 MBd Operation Only, SPDSEL (pin 67) Set High, Non Ping-Pong Mode (PPSEL = 0). HDMP-1512 TOP VIEW 6 ...
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... Figure 20. Typical Receiver Pin Terminations for Applications Using High Speed Serial Copper Links ( DIN). For 1062.5 MBd Operation Only, SPDSEL (pin 71) Set High, Non Ping-Pong Mode (PPSEL = 0). 680 HDMP-1514 TOP VIEW +5.0 V 0.1 µ ...
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... Figure 21. Typical Receiver Pin Terminations for Applications Using High Speed Fiber Links ( DIN). For 1062.5 MBd Operation Only, SPDSEL (pin 71) Set High, Non Ping-Pong Mode (PPSEL = 0). HDMP-1514 TOP VIEW +5.0 V 0.1 µ ...