KU82596SX20 Intel Corporation, KU82596SX20 Datasheet
KU82596SX20
Specifications of KU82596SX20
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KU82596SX20 Summary of contents
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... Plastic Quad Flat Pack (PQFP) Y and PGA Package (See Packaging Specifications Order Number 240800-001 Package Type KU and A) i386 trademark of Intel Corporation Ethernet is a registered trademark of Xerox Corporation CHMOS is a patented process of Intel Corporation November 1995 Order Number 290219-006 IV 290219 – 1 ...
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SX 82596DX and 82596SX High-Performance 32-Bit Local Area Network Coprocessor CONTENTS INTRODUCTION PIN DESCRIPTIONS 82596 AND HOST CPU INTERACTION 82596 BUS INTERFACE 82596 MEMORY ADDRESSING 82596 SYSTEM MEMORY STRUCTURE TRANSMIT AND RECEIVE MEMORY STRUCTURES TRANSMITTING FRAMES RECEIVING FRAMES 82596 ...
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INTRODUCTION The 82596DX intelligent high-performance 32-bit Local Area Network coprocessor 82596DX SX implements the CSMA CD access method and can be configured to support all exist- ing IEEE 802 3 standards TYPEs 10BASE-T 10BASE5 10BASE2 1BASE5 and ...
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SX Figure 2a 82596DX PQFP Pin Configuration 4 290219 – 2 ...
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Figure 2b 82596SX PQFP Pin Configuration 82596DX SX 290219 –34 5 ...
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SX Figure 3a 82596DX PGA Pin View Side 6 290219 – 3 ...
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PGA Cross Reference by Pin Name Address Data Signal Pin No Signal Pin M10 P11 ...
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SX Figure 3b 82596SX PGA Pin View Side 8 290219 –35 ...
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PGA Cross Reference by Pin Name Address Data Signal Pin No Signal Pin M10 P11 ...
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SX PIN DESCRIPTIONS PQFP Symbol Type Pin No CLK2 9 I CLOCK The system clock input provides the fundamental timing for the 82596 It is internally divided by two to generate the 82596 clock All external timing parameters are ...
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PIN DESCRIPTIONS (Continued) PQFP Symbol Type Pin 120 O WRITE READ This dual-function pin is used to distinguish Write and Read cycles This line is floated after a Reset or when the bus is not acquired ADS ...
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SX PIN DESCRIPTIONS (Continued) PQFP Symbol Type Pin No PORT 3 I PORT When this signal is received the 82596 latches the data on the data bus into an internal 32-bit register When the CPU is asserting this signal ...
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PIN DESCRIPTIONS (Continued) PQFP Symbol Type Pin No LPBK 58 O LOOPBACK This TTL-level control signal enables the loopback mode In this mode serial data on the TxD input is routed through the 82C501 internal circuits and back to the ...
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SX 82596 AND HOST CPU INTERACTION The 82596DX SX and the host CPU communicate through shared memory Because of its on-chip DMA capability the 82596 can make data block transfers (buffers and frames) independently of the CPU this greatly ...
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Figure 4 82596 and Host CPU Intervention Figure 5 Bus Throttle Timers Table 1 82596 Memory Addressing Formats Pointer or Offset ISCP ADDRESS 24-Bit Linear SCB ADDRESS Base (24) Command Block Pointers Base (24) Rx Frame Descriptors Base (24) Tx ...
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SX Figure 6 82596 Shared Memory Structure 82596 SYSTEM MEMORY STRUCTURE The Shared Memory structure consists of four parts the Initialization Root the System Control Block the Command List and the Receive Frame Area (see Figure 6) The Initialization ...
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Ready Suspended No Receive Resources etc ) in- terrupt bits (Command Completed Frame Received CU Not Ready and RU Not Ready) and statistical counters The Command List functions as a program for the CU individual commands are placed in memory ...
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SX Figure 7 Frame Reception in the RFA 18 290219 –7 ...
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Figure 8 Simplified Memory Structure Figure 9 Flexible Memory Structure 82596DX SX 290219 – 8 290219 – ...
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SX TRANSMITTING FRAMES The 82596 executes high-level Action Commands from the Command List in system memory Action Commands are fetched and executed in parallel with the host CPU operation thereby significantly improv- ing system performance The format of the ...
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START DESTINATION PREAMBLE FRAME ADDRESS DELIMITER RECEIVING FRAMES To reduce CPU overhead the 82596 is designed to receive frames without CPU supervision The host CPU first sets aside an adequate receive buffer space and then enables the 82596 Receive Unit ...
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SX Figure 13 Receive Frame Area Diagram Figure 14 Receive Frame Descriptor 22 290219 –12 290219 –13 ...
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NETWORK PLANNING AND MAINTENANCE To properly plan operate and maintain a communi- cation network the network management entity must accumulate information on network behavior The 82596 provides a rich set of network-wide diag- nostics that can serve as the basis ...
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SX STATION DIAGNOSTICS AND SELF-TEST The 82596 provides a large set of diagnostic and network management functions These include inter- nal and external loopback and time domain reflec- tometry for locating fault points in the network cable The 82596 ...
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The following diagram illustrates the format of the SCP 31 ODD WORD SYSBUS ...
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SX INTERMEDIATE SYSTEM CONFIGURATION POINTER (ISCP) The ISCP indicates the location of the System Control Block Often the SCP is in ROM and the ISCP is in RAM The CPU loads the SCB address (or an equivalent data structure) ...
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T-ON value is infinite the T-OFF value is zero After the SCP is read the 82596 reads the ISCP and saves the SCB address In 82586 and 32-bit Segmented modes this address is represented as ...
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SX MEMORY ADDRESSING FORMATS The 82596 accesses memory by 32-bit addresses There are two types of 32-bit addresses linear and seg- mented The type of address used depends on the 82596 operating mode and the type of memory structure ...
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The 82596 B stepping supports Big Endian byte ordering for dword word and byte entities in Linear mode only All 82596 B 32-bit address pointers are treated as 32-bit Big Endian entities however the SCB absolute address and statistical counters ...
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SX RECEIVE UNIT (RU) The Receive Unit is the logical unit that receives frames and stores them in memory The RU is modeled as a logical machine that takes at any given time one of the following states Idle ...
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Operation of the Bus Throttle The SCB controls the Bus Throttle timers by providing them with new values and sending the Load and Start timer commands The timers can be operated in both the 32-bit Segmented and Linear modes Reception ...
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SX 31 ODD WORD ACK 0 CUC R RUC COMMAND BLOCK ADDRESS RECEIVE FRAME AREA ADDRESS T-ON TIMER In MONITOR mode these counters change function Command Word 31 ACK 0 CUC These bits specifiy the action to be performed ...
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Bits 20– 22 RUC (3 bits) This field contains the command to the Receive Unit Valid values are 0 NOP (does not alter current state of unit) 1 Start reception of frames The beginning of the RFA is contained in ...
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SX RFA Offset (Address) In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the Receive Frame Area In Linear mode 32-bit linear address for the Receive Frame Area ...
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ACTION COMMANDS AND OPERATING MODES This section lists all the Action Commands of the Command Unit Command Block List (CBL) Each command contains the Command field the Status and Control fields the link to the next Action Command and any ...
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SX where LINK POINTER In the 82586 or 32-bit Segmented modes this is a 16-bit offset to the next Command Block In the Linear mode this is the 32-bit address of the next Command Block EL If set this ...
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Bits 19– 28 Reserved (zero in the 32-bit Segmented and Linear modes) CMD (bits 16– 18) The Address Setup command Value 1h INDIVIDUAL ADDRESS The individual address of the node bytes long The least significant bit of ...
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SX 31 ODD WORD A31 Byte 3 Byte 2 Byte 7 Byte 6 Byte 11 Byte ...
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LOOP BACK PREAMBLE LENGTH MODE BYTE 3 ADR LEN (Bits 0 – 2) Address length (any kind) NO SCR ADD INS (Bit 3) No Source Address Insertion In the 82586 this bit is called AL LOC PREAM LEN (Bits ...
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SX 7 BIT CRC16 PAD STUFF CRC32 BYTE 8 PRM (Bit 0) Promiscuous mode BC DIS (Bit 1) Broadcast disable MANCH NRZ (Bit 2) Manchester or NRZ encoding See specific timing require- ments for TxC in Manchester mode TONO ...
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FDX 0 BYTE 12 FDX (Bit 6) Enables Full Duplex operation DEFAULT 00h 7 DIS BOF MULT IA 1 BYTE 13 MULT IA (Bit 6) Multiple individual address DIS BOF (Bit 7) Disable the backoff algorithm DEFAULT 3Fh ...
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SX A reset (hardware or software) configures the 82596 according to the following defaults Parameter ADDRESS LENGTH A L FIELD LOCATION AUTO RETRANSMIT BITSTUFFING EOC BROADCAST DISABLE CDBSAC CDT FILTER CDT SRC CRC IN MEMORY CRC-16 CRC-32 CRS FILTER ...
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MULTICAST-SETUP This command is used to load the 82596 with the Multicast-IDs that should be accepted As noted previously the filtering done on the Multicast-IDs is not perfect and some unwanted frames may be accepted This command resets the current ...
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SX TRANSMIT This command is used to transmit a frame of user data onto the serial link The format of a Transmit command is as follows 31 ODD WORD ...
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per standard Command Block (see the NOP command for details) OK (Bit 13) Error free completion A (Bit 12) Indicates that the command was abnormally terminated due to CU Abort control command If ...
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SX The interpretation of what is transmitted depends on the No Source Address insertion configuration bit and the memory model being used NOTES 1 The Destination Address and the Length Field are sequential of the Length Field immediately follows ...
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EOF This bit indicates that this TBD is the last one associated with the frame being transmitted It is set by the CPU before transmit SIZE (ACT COUNT) This 14-bit quantity specifies the number of bytes that hold information ...
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SX The format of the Time Domain Reflectometer command is 82586 and 32-Bit Segmented Modes 31 ODD WORD ...
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DUMP This command causes the contents of various 82596 registers to be placed in a memory area specified by the user It is supplied as a 82596 self-diagnostic tool and to provide registers of interest to the user The format ...
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DMA CONTROL REGISTER CONFIGURE BYTES 3 2 CONFIGURE BYTES 5 4 CONFIGURE BYTES 7 6 CONFIGURE BYTES 9 8 CONFIGURE BYTES BYTES ...
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CONFIGURE BYTES CONFIGURE BYTES CONFIGURE BYTES BYTES BYTES CRC BYTES 0 1 LAST T ...
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SX DIAGNOSE The Diagnose Command triggers an internal self-test procedure that checks internal 82596 hardware which includes Exponential Backoff Random Number Generator (Linear Feedback Shift Register) Exponential Backoff Timeout Counter Slot Time Period Counter Collision Number Counter Exponential Backoff ...
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Figure 37 The Receive Frame Area Simplified Memory Structure The first is the Simplified memory structure the data section of the received frame is part of the RFD and is located immediately after the Length Field Receive Buffer Descriptors are ...
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SX Note that this sequence is very useful for monitoring If the 82596 is configured to Save Bad Frames to receive in Promiscuous mode and to use the Simplified memory structure any programmed length of received data can be ...
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Buffers on the receive side can be different lengths The 82596 will not place more bytes into a buffer than indicated in the associated RBD The 82596 will fetch the next RBD before it is needed The 82596 will attempt ...
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SX 31 ODD WORD A15 RBD OFFSET 4th byte SOURCE ADDRESS 6th byte ...
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EL When set this bit indicates that this RFD is the last one on the RDL S When set this bit suspends the RU after receiving the frame SF This bit selects between the Simplified or the Flexible mode ...
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SX LENGTH FIELD The contents of this 2-byte field are user defined In 802 3 it contains the length of the data field It is placed in memory in the same order it is received i e most significant ...
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EOF Indicates that this is the last buffer related to the frame It is cleared by the CPU before starting the RU and is written by the 82596 at the end of reception of the frame F Indicates that ...
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SX PGA PACKAGE THERMAL SPECIFICATION Parameter Thermal Resistance CHARACTERISTICS 10% CLK2 and LE BE have MOS levels (see ...
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A C CHARACTERISTICS 82596DX C-STEP INPUT OUTPUT SYSTEM TIMINGS T These timings assume the C on all outputs unless otherwise specified C L however timings must be derated All timing requirements are given in nanoseconds Symbol Parameter ...
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CHARACTERISTICS (Continued) 82596DX C-STEP INPUT OUTPUT SYSTEM TIMINGS T These timings assume the C on all outputs unless otherwise specified C L however timings must be derated All timing requirements are given in ...
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A C CHARACTERISTICS (Continued) 82596SX C-STEP INPUT OUTPUT SYSTEM TIMINGS T These timings assume the C on all outputs unless otherwise specified C L however timings must be derated All timing requirements are given in nanoseconds Symbol ...
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CHARACTERISTICS (Continued) 82596SX C-STEP INPUT OUTPUT SYSTEM TIMINGS T These timings assume the C on all outputs unless otherwise specified C L however timings must be derated All timing requirements are given in ...
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A C CHARACTERISTICS (Continued) 82596SX C-STEP INPUT OUTPUT SYSTEM TIMINGS T These timings assume the C on all outputs unless otherwise specified C L however timings must be derated All timing requirements are given in nanoseconds Symbol ...
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SX TRANSMIT RECEIVE CLOCK PARAMETERS Symbol Parameter T36 TxC Cycle T38 TxC Rise Time T39 TxC Fall Time T40 TxC High Time T41 TxC Low Time T42 TxD Rise Time T43 TxD Fall Time T44 TxD Transition T45 TxC ...
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TRANSMIT RECEIVE CLOCK PARAMETERS (Continued) Symbol Parameter RECEIVED DATA PARAMETERS (Continued) T60 RxD Rise Time T61 RxD Fall Time CRS AND CDT PARAMETERS T62 CDT Low to TxC HIGH External Collision Detect Setup Time T63 TxC High to CDT Inactive ...
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SX 82596DX SX BUS OPERATION The following figures show thae basic bus cycles for the 82596DX and 82596SX For more details refer to the 32-Bit LAN Components Manual Figure 44 Basic 82596DX Bus Cycles Figure 45 Basic 82596SX Bus ...
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SYSTEM INTERFACE A C TIMING CHARACTERISTICS The measurements should be done – 10 testing inputs are driven for a logic ‘‘1’’ ...
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SX INPUT WAVEFORMS Ts T13 T15 T17 T19 T21 T23 T27 T29 T31 e Th T14 T16 T18 T20 T22 T22a T24 T28 T30 T32 e Figure 48 CA and BREQ Input Timing Figure 49 INT INT Output Timing ...
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Figure 52 Output Valid Delay Timing Figure 53 Output Float Delay Timing Figure 54 PORT Setup and Hold Time 82596DX SX 290219 –25 290219 –26 290219 –27 71 ...
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SX SERIAL A C TIMING CHARACTERISTICS Figure 56 Serial Input Clock Timing Figure 57 Transmit Data Waveforms 72 Figure 55 RESET Input Timing 290219 –28 290219 –29 290219 –30 ...
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Figure 58 Transmit Data Waveforms 290219– 32 Figure 59 Receive Data Waveforms (NRZ) 82596DX SX 290219 –31 290219 –33 Figure 60 Receive Data Waveforms (CRS) 73 ...
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SX OUTLINE DIAGRAMS 132 LEAD CERAMIC PIN GRID ARRAY PACKAGE INTEL TYPE A Family Ceramic Pin Grid Array Package Millimeters Symbol Min Max ...
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Symbol Description Min N Leadcount 68 A Package Height 0 160 0 170 0 160 0 170 0 160 0 170 0 160 0 170 0 160 0 170 0 160 0 170 A1 Standoff 0 020 0 030 0 ...
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SX mm (inch) Figure 61 Principal Dimensions and Datums mm (inch) mm (inch) 76 Figure 62 Molded Details Figure 63 Terminal Details 290219 –37 290219 –38 290219 –39 ...
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Detail J mm (inch) REVISION SUMMARY The following represents the key differences be- tween version -005 and version -006 of the 82596CA Data Sheet 1 A description of the 82596DX SX C-stepping en- hancements was added and the ...