NH82801GBM Intel Corporation, NH82801GBM Datasheet

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NH82801GBM

Manufacturer Part Number
NH82801GBM
Description
82801GBM I/O Controller Hub (ICH7M)
Manufacturer
Intel Corporation
Datasheet
®
Intel
I/O Controller Hub 7 (ICH7)
Family
Datasheet
®
— For the Intel
82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH,
82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O
Controller Hubs
April 2007
Document Number: 307013-003

Related parts for NH82801GBM

NH82801GBM Summary of contents

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Intel I/O Controller Hub 7 (ICH7) Family Datasheet ® — For the Intel 82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH, 82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O Controller Hubs April 2007 Document Number: 307013-003 ...

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... Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...

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Contents 1 Introduction ............................................................................................................ 39 1.1 Overview ......................................................................................................... 42 ® 1.2 Intel ICH7 Family High-Level Component Differences ........................................... 50 2 Signal Description ................................................................................................... 51 2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 55 2.2 PCI Express* (Desktop and Mobile ...

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Peer Cycles .......................................................................................... 102 5.1.6 PCI-to-PCI Bridge Model ........................................................................ 102 5.1.7 IDSEL to Device Number Mapping ........................................................... 103 5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 103 5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) (Desktop and Mobile Only) .......... 103 5.2.1 Interrupt ...

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DMA Operation (D31:F0) .................................................................................. 124 5.6.1 Channel Priority ................................................................................... 124 5.6.1.1 Fixed Priority.......................................................................... 125 5.6.1.2 Rotating Priority ..................................................................... 125 5.6.2 Address Compatibility Mode ................................................................... 125 5.6.3 Summary of DMA Transfer Sizes ............................................................. 125 5.6.3.1 Address Shifting When Programmed for ...

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Level-Triggered Operation......................................................... 142 5.10.4.3 Registers Associated with Front Side Bus Interrupt Delivery .......... 142 5.10.4.4 Interrupt Message Format ........................................................ 142 5.11 Serial Interrupt (D31:F0) .................................................................................. 143 5.11.1 Start Frame ......................................................................................... 143 5.11.2 Data Frames ........................................................................................ 144 5.11.3 Stop Frame ...

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Active Cooling ........................................................................ 167 5.14.9 Event Input Signals and Their Usage ....................................................... 167 5.14.9.1 PWRBTN# (Power Button) ........................................................ 167 5.14.9.2 RI# (Ring Indicator)................................................................ 168 5.14.9.3 PME# (PCI Power Management Event) ....................................... 169 5.14.9.4 SYS_RESET# Signal ................................................................ 169 5.14.9.5 THRMTRIP# ...

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Intel 5.17.4 Power Management Operation ................................................................ 194 5.17.4.1 Power State Mappings.............................................................. 194 5.17.4.2 Power State Transitions ............................................................ 195 5.17.4.3 SMI Trapping (APM) ................................................................. 196 5.17.5 SATA LED ............................................................................................ 196 5.17.6 AHCI Operation (Intel 5.17.7 Serial ATA Reference Clock Low ...

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USB 2.0 Legacy Keyboard Operation ....................................................... 214 5.20.10USB 2.0 Based Debug Port .................................................................... 214 5.20.10.1 Theory of Operation ............................................................... 215 5.21 SMBus Controller (D31:F3) ............................................................................... 219 5.21.1 Host Controller..................................................................................... 220 5.21.1.1 Command Protocols ................................................................ 220 5.21.2 Bus Arbitration..................................................................................... 224 ...

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CE-like On/Off ...................................................................................... 249 ® 5.26.3 Intel Quick Resume Technology Signals (ICH7DH Only)............................ 250 5.26.4 Power Button Sequence (ICH7DH Only) ................................................... 250 5.27 Feature Capability Mechanism ........................................................................... 251 6 Register and Memory Mapping ............................................................................... 253 6.1 PCI Devices and ...

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TCTL—TCO Configuration Register........................................................... 282 7.1.41 D31IP—Device 31 Interrupt Pin Register.................................................. 283 7.1.42 D30IP—Device 30 Interrupt Pin Register.................................................. 284 7.1.43 D29IP—Device 29 Interrupt Pin Register.................................................. 285 7.1.44 D28IP—Device 28 Interrupt Pin Register (Desktop and Mobile Only) ............ 286 7.1.45 D27IP—Device ...

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PORT—PORT Interface Register (LAN Controller—B1:D8:F0) ....................... 319 8.2.5 EEPROM_CNTL—EEPROM Control Register (LAN Controller—B1:D8:F0)......... 321 8.2.6 MDI_CNTL—Management Data Interface (MDI) Control Register (LAN Controller—B1:D8:F0) ....................................................... 322 8.2.7 REC_DMA_BC—Receive DMA Byte Count Register (LAN Controller—B1:D8:F0) ................................................................... 322 8.2.8 EREC_INTR—Early Receive Interrupt ...

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PSTS—PCI Status Register (PCI-PCI—D30:F0).......................................... 347 9.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)............................ 349 9.1.6 CC—Class Code Register (PCI-PCI—D30:F0) ............................................ 349 9.1.7 PMLT—Primary Master Latency Timer Register (PCI-PCI—D30:F0) ............... 350 9.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) ................................. 350 9.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ...

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Hub Select 2 Register (LPC I/F—D31:F0) .................. 378 10.1.28FWH_DEC_EN1—Firmware Hub Decode Enable Register (LPC I/F—D31:F0) .. 378 10.1.29BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) .............................. 381 10.1.30FDCAP—Feature Detection Capability ID (LPC I/F—D31:F0) ........................ 382 10.1.31FDLEN—Feature Detection Capability Length (LPC I/F—D31:F0) .................. ...

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RTC_REGD—Register D (Flag Register) (LPC I/F—D31:F0) ............ 414 10.7 Processor Interface Registers (LPC I/F—D31:F0) ................................................. 415 10.7.1 NMI_SC—NMI Status and Control Register (LPC I/F—D31:F0) .................... 415 10.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) Register (LPC I/F—D31:F0).................................................................... 416 10.7.3 ...

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TCO1_STS—TCO1 Status Register ........................................................... 457 10.9.5 TCO2_STS—TCO2 Status Register ........................................................... 459 10.9.6 TCO1_CNT—TCO1 Control Register .......................................................... 460 10.9.7 TCO2_CNT—TCO2 Control Register .......................................................... 461 10.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers........................................ 461 10.9.9 TCO_WDCNT—TCO Watchdog Control Register .......................................... 462 10.9.10SW_IRQ_GEN—Software IRQ Generation ...

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RID—Revision Identification Register (SATA—D31:F2) ............................... 493 12.1.6 PI—Programming Interface Register (SATA–D31:F2) ................................. 493 12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h........... 493 12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h........... 494 12.1.6.3 When Sub Class ...

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FIS Control/Status Register (SATA–D31:F2) ............................ 517 12.1.44BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ......................... 518 12.1.45BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ......................... 519 12.2 Bus Master IDE I/O Registers (D31:F2)............................................................... 519 12.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) ........................... 520 ...

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Management Control/ Status Register (USB EHCI—D29:F7) ...................................................... 553 13.1.20DEBUG_CAPID—Debug Port Capability ID Register (USB EHCI—D29:F7) ...... 554 13.1.21NXT_PTR2—Next Item Pointer #2 Register (USB EHCI—D29:F7) ................ 554 13.1.22DEBUG_BASE—Debug Port Base Offset Register (USB EHCI—D29:F7) ......... 554 13.1.23USB_RELNUM—USB Release Number Register ...

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XMIT_SLVA—Transmit Slave Address Register (SMBUS—D31:F3)................. 593 14.2.5 HST_D0—Host Data 0 Register (SMBUS—D31:F3)..................................... 593 14.2.6 HST_D1—Host Data 1 Register (SMBUS—D31:F3)..................................... 593 14.2.7 Host_BLOCK_DB—Host Block Data Byte Register (SMBUS—D31:F3) ............ 594 14.2.8 PEC—Packet Error Check (PEC) Register (SMBUS—D31:F3) ........................ 594 14.2.9 ...

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AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) ................. 619 16.1 AC ’97 Audio PCI Configuration Space (Audio—D30:F2) ........................................ 619 16.1.1 VID—Vendor Identification Register (Audio—D30:F2) ................................ 620 16.1.2 DID—Device Identification Register (Audio—D30:F2)................................. 620 16.1.3 PCICMD—PCI Command Register ...

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Pointer Register (Modem—D30:F3).......................... 652 17.1.15INT_LN—Interrupt Line Register (Modem—D30:F3) ................................... 653 17.1.16INT_PIN—Interrupt Pin Register (Modem—D30:F3) ................................... 653 17.1.17PID—PCI Power Management Capability Identification Register (Modem—D30:F3) .................................................................... 653 17.1.18PC—Power Management Capabilities Register (Modem—D30:F3) ................. 654 17.1.19PCS—Power Management Control and Status Register (Modem—D30:F3) ...

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Memory Limit Upper 32 Bits Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................... 674 18.1.19CAPP—Capabilities List Pointer Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 674 18.1.20INTR—Interrupt Information Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 675 18.1.21BCTRL—Bridge Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 676 18.1.22CLIST—Capabilities List Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 677 18.1.23XCAP—PCI Express* Capabilities Register ...

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Channel Capability 2 Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 695 18.1.50PVC—Port Virtual Channel Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 695 18.1.51PVS — Port Virtual Channel Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 696 18.1.52V0CAP — Virtual Channel 0 Resource Capability Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... ...

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Timer Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 710 19.1.11HEADTYP—Header Type Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 711 19.1.12HDBARL—Intel ® (Intel High Definition Audio—D27:F0) ................................................... 711 19.1.13HDBARU—Intel ® (Intel High Definition Audio Controller—D27:F0)..................................... 711 19.1.14SVID—Subsystem Vendor Identification Register ...

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Port VC Capability Register 2 ® (Intel High Definition Audio Controller—D27:F0) ..................................... 722 19.1.39PVCCTL — Port VC Control Register ® (Intel High Definition Audio Controller—D27:F0) ..................................... 723 19.1.40PVCSTS—Port VC Status Register ® (Intel High Definition Audio Controller—D27:F0) ..................................... ...

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Status Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 740 19.2.15WALCLK—Wall Clock Counter Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 741 19.2.16SSYNC—Stream Synchronization Register ® (Intel High Definition Audio Controller—D27:F0)..................................... 741 19.2.17CORBLBASE—CORB Lower Base Address Register ® (Intel High Definition ...

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Descriptor FIFO Size Register ® (Intel High Definition Audio Controller—D27:F0) ..................................... 755 19.2.43SDFMT—Stream Descriptor Format Register ® (Intel High Definition Audio Controller—D27:F0) ..................................... 756 19.2.44SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register (Intel 19.2.45SDBDPU—Stream Descriptor Buffer Descriptor ...

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Figures 2-1 Interface Signals Block Diagram (Desktop Only)........................................................... 52 2-2 Interface Signals Block Diagram (Mobile Only) ............................................................ 53 2-3 Interface Signals Block Diagram (Ultra Mobile Only) ..................................................... 54 2-4 Example External RTC Circuit..................................................................................... 78 4-1 Desktop Only Conceptual System Clock ...

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Timings (Mobile/Ultra Mobile Only) .................................................... 831 23-28C0 Timings (Mobile/Ultra Mobile Only) .................................................... 832 23-29C0 Timings (Mobile/Ultra Mobile Only) .................................................... 832 23-30AC ’97 Data Input and Output Timings ...

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Start Field Bit Definitions ........................................................................................ 119 5-7 Cycle Type Bit Definitions........................................................................................ 120 5-8 Transfer Size Bit Definition ...................................................................................... 120 5-9 SYNC Bit Definition................................................................................................. 121 5-10DMA Transfer Size.................................................................................................. 126 5-11Address Shifting in 16-Bit I/O DMA Transfers ............................................................. 126 5-12Counter Operating ...

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Implementation Options .................................................................................... 245 5-62Required Commands and Opcodes ............................................................................ 247 ® 5-63Intel ICH7 Standard SPI Commands ....................................................................... 247 5-64Flash Protection Mechanism Summary....................................................................... 248 6-1 PCI Devices and Functions ....................................................................................... 254 6-2 Fixed I/O Ranges Decoded by Intel 6-3 Variable ...

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High Definition Audio PCI Register Address Map ® (Intel High Definition Audio D27:F0)....................................................................... 705 ® 19-2Intel High Definition Audio PCI Register Address Map ® (Intel High Definition Audio D27:F0)....................................................................... 728 20-1Memory-Mapped Registers ...................................................................................... 759 21-1Serial Peripheral Interface (SPI) ...

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Revision History Revision -001 • Initial release -002 • Added specificaitons for ICH7DH, ICH7-M, and ICH7-M DH • Added specifications for the ICH7-U -003 • Added Documentation Changes/Specification Changes from Spec Update Revision -020. 34 Description § Intel Date April ...

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Intel ICH7 Family Features Direct Media Interface — 10 Gb/s each direction, full duplex — Transparent to software PCI Express* (Desktop and Mobile Only) — 4 PCI Express root ports — NEW: 2 Additional PCI Express root ports (ICH7R/ ...

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SMBus — Flexible SMBus/SMLink architecture to optimize for ASF — Provides independent manageability bus through SMLink interface — Supports SMBus 2.0 Specification — Host interface allows processor to communicate via SMBus — Slave interface allows an internal or external Microcontroller ...

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Mobile Configuration Ultra Mobile Configuration ® Intel ICH7 Family Datasheet DMI (To (G)MCH) USB 2.0 (Supports 8 USB ports) IDE SATA (2 ports) ® Intel ICH7-M AC’97/Intel® High Definition Audio Codec(s) PCI Bus PCI Express x1 LAN Connect GPIO LPC ...

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Intel ICH7 Family Datasheet ...

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Introduction 1 Introduction This document is intended for Original Equipment Manufacturers and BIOS vendors ® creating Intel I/O Controller Hub 7 (ICH7) Family based products. This document is the datasheet for the following: ® • Intel 82801GB ICH7 (ICH7) ® ...

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Table 1-1. Industry Specifications System Management Bus Specification, Version 2.0 (SMBus) PCI Local Bus Specification, Revision 2.3 (PCI) PCI Mobile Design Guide, Revision 1.1 PCI Power Management Specification, Revision 1.1 Universal Serial Bus Specification (USB), Revision 2.0 Advanced Configuration and ...

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Introduction Chapter 6. Register and Memory Mappings Chapter 6 provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory ranges decoded by the ICH7. Chapter 7. Chipset Configuration Registers Chapter 7 provides a detailed description of ...

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Chapter 20. High Precision Event Timers Registers Chapter 20 provides a detailed description of all registers that reside in the multimedia timer memory mapped register space. Chapter 21. Serial Peripheral Interface Registers Chapter 21 provides a detailed description of all ...

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Introduction The ICH7 incorporates a variety of PCI functions that are divided into six logical devices (B0:D27, B0:D28, B0:D29, B0:D30, B0:D31 and B1:D8) as listed in the DMI-to-PCI bridge and the AC ’97 Audio and Modem controller functions, D31 contains ...

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PCI Express* Interface (Desktop and Mobile Only) The ICH7R, ICH7DH, ICH7-M DH have six PCI Express root ports and the ICH7 and ICH7-M have four PCI Express root ports (ports 1-4), supporting the PCI Express Base Specification, Revision 1.0a. PCI ...

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Introduction IDE Interface (Bus Master Capability and Synchronous DMA Mode) The fast IDE interface supports up to two IDE devices (one device on Ultra Mobile) providing an interface for IDE hard disks and ATAPI devices. Each IDE device can have ...

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Universal Serial Bus (USB) Controller The ICH7 contains an Enhanced Host Controller Interface (EHCI) host controller that supports USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster than full-speed USB. The ...

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Introduction RTC The ICH7 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered ...

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Manageability In addition to Intel AMT the ICH7 integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and ...

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Introduction ® Intel High Definition Audio Controller ® The Intel High Definition Audio Specification defines a digital interface that can be used to attach different types of codecs, such as audio and modem codecs. The ICH7 Intel HD Audio digital ...

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Intel ICH7 Family High-Level Component Differences ® Table 1-3. Intel ICH7 Desktop/Server Family Product Name ® Intel ICH7 Base (ICH7) ICH7 Digital Home (ICH7DH) ICH7 RAID (ICH7R) NOTES: 1. Feature capability can be read in D31:F0:Offset E4h. 2. ...

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Signal Description 2 Signal Description This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. interface signals for the Intel ICH7DH. Figure 2-2 82801GHM ICH7-M DH. U. The “#” ...

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Figure 2-1. Interface Signals Block Diagram (Desktop Only) AD[31:0] C/BE[3:0]# DEVSEL# FRAME# REQ[3:0]# REQ[4]# / GPIO[22] REQ[5]# / GPIO[1] GNT[3:0]# GNT[4]# / GPIO[48] GNT[5]# / GPIO[17] PCIRST# PLOCK# CPUSLP# IGNNE# INIT3_3V# STPCLK# A20GATE CPUPWRGD / GPIO[49] SPI_CS# SPI_MISO SPI_MOSI SPI_ARB ...

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Signal Description Figure 2-2. Interface Signals Block Diagram (Mobile Only) REQ[4]# / GPIO[22] REQ[5]# / GPIO[1] GNT[4]# / GPIO[48] GNT[5]# / GPIO[17] CPUPWRGD / GPIO[49] PIRQ[H:E]# / GPIO[5:2] OC[5]# / GPIO[29] OC[6]# / GPIO[30] OC[7]# / GPIO[31] SATA_CLKP, SATA_CLKN DMI_CLKP, ...

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Figure 2-3. Interface Signals Block Diagram (Ultra Mobile Only) C/BE[3:0]# DEVSEL# FRAME# REQ4# / GPIO[22] REQ5# / GPIO[1] GNT4# / GPIO[48] GNT5# / GPIO[17] CLKRUN# PCIRST# PLOCK# IGNNE# INIT3_3# STPCLK# A20GATE CPUPWRGD / GPIO[49] DPSLP# SERIRQ PIRQ[H:E]# / GPIO[5:2] USBP[7:0]P ...

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Signal Description 2.1 Direct Media Interface (DMI) to Host Controller Table 2-1. Direct Media Interface Signals Name Type DMI[0:1]TXP, DMI[0:1]TXN O DMI[2:3]TXP, DMI[2:3]TXN (Desktop and Mobile Only) DMI[0:1]RXP, DMI[0:1]RXN I DMI[2:3]RXP, DMI[2:3]RXN (Desktop and Mobile Only) DMI_ZCOMP I DMI_IRCOMP O ...

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Platform LAN Connect Interface (Desktop and Mobile Only) Table 2-3. Platform LAN Connect Interface Signals Name Type LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC 2.4 EEPROM Interface (Desktop and Mobile Only) Table 2-4. EEPROM Interface Signals Name Type EE_SHCLK O EE_DIN I ...

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Signal Description 2.6 PCI Interface Table 2-6. PCI Interface Signals (Sheet Name Type AD[31:0] I/O C/BE[3:0]# I/O DEVSEL# I/O FRAME# I/O IRDY# I/O ® Intel ICH7 Family Datasheet Description PCI Address/Data: AD[31: multiplexed address and ...

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Table 2-6. PCI Interface Signals (Sheet Name Type TRDY# I/O STOP# I/O PAR I/O PERR# I/O REQ[3:0]# REQ4# / GPIO22 I REQ5# / GPIO1 GNT[3:0]# GNT4# / GPIO48 O GNT5# / GPIO17# PCICLK I PCIRST ...

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Signal Description Table 2-6. PCI Interface Signals (Sheet Name Type PLOCK# I/O SERR# I/OD PME# I/OD 2.7 Serial ATA Interface (Desktop and Mobile Only) Table 2-7. Serial ATA Interface Signals (Sheet Name SATA0TXP SATA0TXN ...

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Table 2-7. Serial ATA Interface Signals (Sheet Name SATA0GP / GPIO21 SATA1GP (Desktop Only) / GPIO19 SATA2GP / GPIO36 SATA3GP (Desktop Only) / GPIO37 SATALED# (Native) SATACLKREQ#/ GPIO35 I/O (GP) 2.8 IDE Interface Table 2-8. IDE Interface ...

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Signal Description Table 2-8. IDE Interface Signals (Sheet Name Type DDREQ DDACK# DIOR# / (DWSTB / RDMARDY#) DIOW# / (DSTOP) IORDY / (DRSTB / WDMARDY#) ® Intel ICH7 Family Datasheet Description IDE Device DMA Request: This input ...

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LPC Interface Table 2-9. LPC Interface Signals Name Type LAD[3:0] / I/O FWH[3:0] LFRAME FWH4 LDRQ0# LDRQ1# / GPIO23 I (Desktop and Mobile only) 2.10 Interrupt Interface Table 2-10. Interrupt Signals Name Type SERIRQ I/O PIRQ[D:A]# (Desktop ...

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Signal Description 2.11 USB Interface Table 2-11. USB Interface Signals Name USBP0P, USBP0N, USBP1P, USBP1N USBP2P, USBP2N, USBP3P, USBP3N USBP4P, USBP4N, USBP5P, USBP5N USBP6P, USBP6N, USBP7P, USBP7N OC[4:0]# OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31 USBRBIAS USBRBIAS# ® ...

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Power Management Interface Table 2-12. Power Management Interface Signals (Sheet Name Type PLTRST# THRM# THRMTRIP# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# (Desktop and Mobile Only) 64 Description ® Platform Reset: The Intel ICH7 asserts PLTRST# to ...

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Signal Description Table 2-12. Power Management Interface Signals (Sheet Name Type SYS_RESET# RSMRST# LAN_RST# (Desktop and Mobile Only) WAKE# MCH_SYNC# SUS_STAT# / LPCPD# SUSCLK VRMPWRGD BM_BUSY# (Mobile/Ultra Mobile Only) / GPIO0 (Desktop Only) CLKRUN# (Mobile/Ultra Mobile Only)/ ...

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Table 2-12. Power Management Interface Signals (Sheet Name Type STP_CPU# (Mobile/Ultra Mobile Only) / GPIO20 (Desktop Only) BATLOW# (Mobile/Ultra Mobile Only) / TP0 (Desktop Only) DPRSLPVR (Mobile/Ultra Mobile Only) / GPIO16 (Desktop Only) DPRSTP# (Mobile/Ultra Mobile Only) ...

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Signal Description Table 2-13. Processor Interface Signals (Sheet Name Type IGNNE# O INIT# O INIT3_3V# (Desktop O and Mobile Only) INTR O NMI O SMI# O STPCLK# O RCIN# I ® Intel ICH7 Family Datasheet Description Ignore ...

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Table 2-13. Processor Interface Signals (Sheet Name Type A20GATE I CPUPWRGD O / GPIO49 DPSLP# (Mobile/Ultra Mobile Only TP2 (Desktop Only) 2.14 SMBus Interface Table 2-14. SM Bus Interface Signals Name SMBDATA SMBCLK SMBALERT# / ...

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Signal Description 2.16 Real Time Clock Interface Table 2-16. Real Time Clock Interface Name Type RTCX1 Special RTCX2 Special 2.17 Other Clocks Table 2-17. Other Clocks Name Type CLK14 I CLK48 I SATA_CLKP SATA_CLKN I (Desktop and Mobile Only) DMI_CLKP, ...

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Miscellaneous Signals Table 2-18. Miscellaneous Signals Name Type INTVRMEN (Desktop and Mobile Only) SPKR O RTCRST# (Desktop and Mobile Only) TP0 (Desktop Only) / BATLOW# (Mobile/Ultra Mobile Only) TP1 (Desktop Only DPRSTP# (Mobile/Ultra Mobile Only) TP2 (Desktop ...

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Signal Description 2.19 AC ’97/Intel Note: AC ‘97 is not supported on Ultra Mobile. ® Table 2-19. AC ’97/Intel High Definition Audio Link Signals 1,2 Name ACZ_RST# ACZ_SYNC ACZ_BIT_CLK ACZ_SDOUT ACZ_SDIN[2:0] AZ_DOCK_EN# (Mobile Only) / GPIO33 AZ_DOCK_RST# (Mobile Only) / ...

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Serial Peripheral Interface (SPI) (Desktop and Mobile Only) Table 2-20. Serial Peripheral Interface (SPI) Signals Name Type SPI_CS# SPI_MISO SPI_MOSI SPI_ARB SPI_CLK ® 2.21 Intel Quick Resume Technology (Intel Only) Signal Name EL_RSVD / GPIO26 EL_STATE[1:0] / GPIO[28:27] 2.22 ...

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Signal Description Table 2-21. General Purpose I/O Signals (Sheet 1,2 Name Type GPIO36 (Desktop and I/O Mobile Only) GPIO35 (Desktop and I/O Mobile Only) GPIO34 (Desktop and I/O Mobile Only) GPIO33 (Desktop and I/O Mobile Only) GPIO32 ...

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Table 2-21. General Purpose I/O Signals (Sheet 1,2 Name Type GPIO19 (Desktop and I/O Mobile Only) GPIO18 I/O (Desktop Only) GPIO17 I/O GPIO16 I/O GPIO[15:12] I/O GPIO11 I/O GPIO[10:8] I/O GPIO[7:6] I/O GPIO[5:2] I/OD GPIO1 I/O GPIO0 ...

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Signal Description Table 2-22. Power and Ground Signals (Sheet Name V5REF1 These pins provide the reference for 5 V tolerance on core well inputs (1 pin). (Ultra Mobile This power may be shut off in S3, S4, ...

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Table 2-22. Power and Ground Signals (Sheet Name This pin provides the 3.3 V (can drop to 2.0 V min state) supply for the RTC well (1 pin). This power is not expected to be ...

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Signal Description Table 2-23. Functional Strap Definitions (Sheet Signal Usage EE_DOUT (Desktop Reserved and Mobile Only) GNT2# Reserved Top-Block GNT3# Swap Override GNT5# / Boot BIOS GPIO17#, Destination GNT4# / Selection GPIO48 GPIO16 (Desktop Only) / Reserved ...

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Table 2-23. Functional Strap Definitions (Sheet Signal Usage LINKALERT# (Desktop Reserved and Mobile Only) XOR Chain REQ[4:1]# Selection SATALED# (Desktop Reserved and Mobile Only) SPKR No Reboot XOR Chain TP3 Entrance NOTE: See Section 2.24.2 External RTC ...

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Intel ICH7 Pin States ® 3 Intel 3.1 Integrated Pull-Ups and Pull-Downs Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet Signal ACZ_BIT_CLK, AC ‘97 (Desktop and Mobile Only) ACZ_RST#, AC ‘97 (Desktop and Mobile Only) ACZ_SDIN[2:0], ...

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Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet Signal SPI_ARB (Desktop and Mobile Only) SPI_CLK (Desktop and Mobile Only) SPKR TP3 USB[7:0] [P,N] NOTES: 1. The pull-down resistors on ACZ_BIT_CLK (AC ‘97) and ACZ_RST# are enabled when ...

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Intel ICH7 Pin States 3.3 Output and I/O Signals Planes and States Table 3-3 and Table 3-4 signals, as well as the state at various times. Within the table, the following terms are used: “High-Z” “High” “Low” “Defined” “Undefined” ...

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Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only Configurations (Sheet Signal Name AD[31:0] C/BE[3:0]# DEVSEL# FRAME# GNT[3:0]# GNT4# / GPIO48 GNT5# / GPIO17 IRDY#, TRDY# PAR PCIRST# PERR# PLOCK# STOP# LAD[3:0] ...

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Intel ICH7 Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only Configurations (Sheet Signal Name SATARBIAS SATA3GP / GPIO37 SATA2GP / GPIO36 SATA1GP / GPIO19 SATA0GP / GPIO21 SATACLKREQ# ...

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Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only Configurations (Sheet Signal Name STPCLK# SMBCLK, SMBDATA SMLINK[1:0] LINKALERT# SPKR ACZ_RST# ACZ_SDOUT ACZ_SYNC ACZ_RST# ACZ_SDOUT ACZ_SYNC ACZ_BIT_CLK GPIO[7:6, 0] GPIO[15:12,10:8] GPIO16 GPIO18 GPIO20 ...

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Intel ICH7 Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only Configurations (Sheet Signal Name GPIO[39:38] SPI_CS# SPI_MOSI SPI_CLK Intel EL_RSVD / GPIO26 EL_STATE[1:0] / GPIO[28:27] NOTES: 1. The ...

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Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only Configurations (Sheet Power Signal Name Plane PETp[6:1], Core PETn[6:1] DMI[3:0]TXP, Core DMI[3:0]TXN AD[31:0] Core C/BE[3:0]# Core CLKRUN# Core DEVSEL# Core FRAME# Core ...

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Intel ICH7 Pin States Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only Configurations (Sheet Power Signal Name Plane DD[7] Core DDACK# Core DIOR#, DIOW# Core SATA[0]TXP, SATA[0]TXN Core SATA[2]TXP, ...

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Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only Configurations (Sheet Power Signal Name Plane A20M# Core CPUPWRGD / Core GPIO49 IGNNE# Core INIT# Core INIT3_3V# Core INTR Core NMI Core ...

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Intel ICH7 Pin States Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only Configurations (Sheet Power Signal Name Plane ACZ_BIT_CLK Core AZ_DOCK_RST# / Core GPIO34 AZ_DOCK_EN# / Core GPIO33 GPIO[7:6] ...

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Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running. 12. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 ...

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Intel ICH7 Pin States Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet Signal Name INTVRMEN IORDY LAN_CLK LAN_RST# LAN_RXD[2:0] LDRQ0# 2 LDRQ1# / GPIO23 MCH_SYNC# OC[7:0]# PCICLK PME# PWRBTN# PWROK RCIN# REQ[3:0]#, ...

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Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet Signal Name WAKE# SPI_MISO SPI_ARB NOTES signal states are platform implementation specific, as some external components HOT and interfaces may be ...

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Intel ICH7 Pin States Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations (Sheet Power Signal Name IORDY LAN_CLK (Mobile Only) LAN_RST# Suspend (Mobile Only) LAN_RXD[2:0] (Mobile Only) LDRQ0# LDRQ1 GPIO23 ...

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Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations (Sheet Power Signal Name THRMTRIP# TP3 Suspend USBRBIAS# Suspend VRMPWRGD WAKE# Suspend SPI_MISO Suspend (Mobile Only) SPI_ARB Suspend (Mobile Only) NOTES ...

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Intel ICH7 and System Clock Domains ® 4 Intel Domains Table 4-1 shows the system clock domains. assumed connection of the various system components, including the clock generator in desktop and mobile/ultra mobile systems. For complete details of the ...

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Figure 4-1. Desktop Only Conceptual System Clock Diagram ® Intel ICH7 32 kHz XTAL Figure 4-2. Mobile Only Conceptual Clock Diagram Intel ICH7-M 32 kHz XTAL SUSCLK# (32 kHz MHz 14.31818 MHz 48.000 MHz 100 MHz Diff. Pair ...

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Intel ICH7 and System Clock Domains Figure 4-3. Ultra Mobile Only Conceptual Clock Diagram ® Intel ICH7-U 32 kHz XTAL ® Intel ICH7 Family Datasheet 33 MHz 14.31818 MHz 48.000 MHz Clock Generator STP_CPU# STP_PCI# DMI 100 MHz Diff ...

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Intel ICH7 and System Clock Domains ® Intel ICH7 Family Datasheet ...

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Functional Description 5 Functional Description This chapter describes the functions and interfaces of the ICH7 family. 5.1 PCI-to-PCI Bridge (D30:F0) The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the ICH7 implements the ...

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I/O Reads and Writes The bridge generates single DW I/O read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is retried, the cycle is kept ...

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Functional Description 5.1.2.8 Memory and I/O Decode to PCI The PCI bridge in the ICH7 is a subtractive decode agent, which follows the following rules when forwarding a cycle from DMI to the PCI interface: • The PCI bridge will ...

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Peer Cycles The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, IO, and configuration cycle types. Peer cycles are only allowed through VC0, and are enabled with the following bits: • BPC.PDE (D30:F0:Offset 4Ch:bit ...

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Functional Description 5.1.7 IDSEL to Device Number Mapping When addressing devices on the external PCI bus (with the PCI slots), the ICH7 asserts one address signal as an IDSEL. When accessing device 0, the ICH7 asserts AD16. When accessing Device ...

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Table 5-3. MSI vs. PCI IRQ Actions All bits 0 One or more bits set to 1 One or more bits set to 1, new bit gets set to 1 One or more bits set to 1, software clears some ...

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Functional Description RCTL.PIE (D28:F0/F1/F2/F3/F4/F5:Offset 5Ch:bit 3), an interrupt will be generated. This interrupt can be either a pin or a MSI if MSI is enabled via MC.MSIE (D28:F0/F1/ F2/F3/F4/F5:Offset 82h:bit 0). See If this is a subsequent message received (RSTS.PS ...

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Hot-Plug Each root port implements a Hot-Plug controller which performs the following: • Messages to turn on / off / blink LEDs • Presence and attention button detection • Interrupt generation The root port only allows Hot-Plug with modules ...

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Functional Description 5.2.4.3 Attention Button Detection When an attached device is ejected, an attention button could be pressed by the user. This attention button press will result in a the PCI Express message “Attention_Button_Pressed” from the device. Upon receiving this ...

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LAN Controller (B1:D8:F0) (Desktop and Mobile Only) The ICH7’s integrated LAN controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN controller to perform high-speed data transfers over the PCI bus. Its ...

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Functional Description 5.3.1.1 Bus Slave Operation The ICH7 integrated LAN controller serves as a target device in one of the following cases: • Processor accesses to the LAN controller System Control Block (SCB) Control/ Status Registers (CSR) • Processor accesses ...

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System Error: The LAN controller reports parity error during the address phase using the SERR# pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit are not set, the LAN controller only ...

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Functional Description 5.3.1.5 Wake-Up Events There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two events are detailed below. Note: If the Wake on LAN bit in the EEPROM is not set, wake-up events are ...

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Wake on LAN* (Preboot Wake-Up) The LAN controller enters Wake on LAN mode after reset if the Wake on LAN bit in the EEPROM is set. At this point, the LAN controller is in the D0u state. When the ...

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Functional Description 5.3.3 CSMA/CD Unit The ICH7 integrated LAN controller CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It performs all the CSMA/CD protocol functions (e.g., transmission, reception, collision handling, ...

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TCO Functionality The ICH7 integrated LAN controller supports management communication to reduce Total Cost of Ownership (TCO). The SMBus is used as an interface between the ASF controller and the integrated TCO host controller. There are two different types ...

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Functional Description Dx>0 Power State: While the ICH7 powerdown state, it may receive TCO packets or all directly to the TCO controller. Receiving TCO packets is enabled by the set Receive enable command from the TCO controller. ...

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A major advantage of ASF is that it provides these services during the time that software is unable (e.g., during a low- power state, during boot-up, or during an operating system hang) ...

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Functional Description • ASF Compliance — Compliant with the Alert Standard Format (ASF) Specification, Version 1.03 - PET Compliant Packets - RMCP - Legacy Sensor Polling - ASF Sensor Polling - Remote Control Sensor Support • Advanced Features / Miscellaneous ...

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ASF Software Support ASF requires software support to make a complete solution. The following software is used as part of the complete solution. • ASF Configuration driver / application • Network Driver • BIOS Support for SMBIOS, SMBus ARP, ...

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Functional Description 5.5.1.1 LPC Cycle Types The ICH7 implements the following cycle types as described in Table 5-5. LPC Cycle Types Supported Cycle Type I/O Read I/O Write DMA Read (Desktop and Mobile Only) DMA Write (Desktop and Mobile Only) ...

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Cycle Type / Direction (CYCTYPE + DIR) The ICH7 drives bit 0 of this field to 0. Peripherals running bus master cycles must also drive bit Table 5-7 Table 5-7. Cycle Type Bit Definitions Bits[3:2] Bit1 ...

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Functional Description 5.5.1.5 SYNC Valid values for the SYNC field are shown in Table 5-9. SYNC Bit Definition 1,2 Bits[3:0] Ready: SYNC achieved with no error. For DMA transfers on desktop and mobile 0000 components, this also indicates DMA request ...

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LFRAME# Usage The ICH7 follows the usage of LFRAME# as defined in the Low Pin Count Interface Specification, Revision 1.1. The ICH7 performs an abort for the following cases (possible failure cases): • ICH7 starts a Memory, I/O, or ...

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Functional Description 5.5.1.12 Configuration and Intel LPC Interface Decoders To allow the I/O cycles and memory mapped cycles the LPC interface, the ICH7 includes several decoders. During configuration, the ICH7 must be programmed with the same decode ...

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DMA Operation (D31:F0) Note: For ICH7-U Ultra Mobile, LPC DMA is not supported. The ICH7 supports LPC DMA using the ICH7’s DMA controller. The DMA controller has registers that are fixed in the lower I/O space. ...

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Functional Description 5.6.1.1 Fixed Priority The initial fixed priority structure is as follows: High priority Low priority The fixed priority ordering and 7. In this scheme, channel 0 has ...

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Address Shifting When Programmed for 16-Bit I/O Count by Words Table 5-10. DMA Transfer Size DMA Device Date Size And Word Count 8-Bit I/O, Count By Bytes 16-Bit I/O, Count By Words (Address Shifted) The ICH7 maintains compatibility with ...

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Functional Description 5.7 LPC DMA (Desktop and Mobile Only) DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on ...

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In these cases, the peripheral wishes to stop further DMA activity. It may sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was seen by the ICH7, there is no assurance ...

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Functional Description 5.7.6 DMA Request Deassertion An end of transfer is communicated to the ICH7 through a special SYNC field transmitted by the peripheral. An LPC device must not attempt to signal the end of a transfer by deasserting LDREQ#. ...

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Under default operation, the host only performs 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. The method by which this communication between host and peripheral through system BIOS is performed is beyond the scope of this specification. ...

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Functional Description 5.8.1 Timer Programming The counter/timers are programmed in the following fashion: 1. Write a control word to select a counter. 2. Write an initial count for that counter. 3. Load the least and/or most significant bytes (as required ...

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Reading from the Interval Timer It is often desirable to read the value of a counter without disturbing the count in progress. There are three methods for reading the counters: a simple read operation, counter Latch command, and the ...

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Functional Description Both count and status of the selected counters may be latched simultaneously. This is functionally the same as issuing two consecutive, separate Read Back commands. If multiple count and/or status Read Back commands are issued to the same ...

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Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and IRQ13. Note: Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH7. In the following descriptions of the 8259s, the interrupt levels are ...

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Functional Description 5.9.1.3 Hardware/Software Interrupt Sequence 1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to ...

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ICW2 The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. A different base is selected for each interrupt controller. 5.9.2.3 ICW3 The third ...

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Functional Description 5.9.4.2 Special Fully-Nested Mode This mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode is programmed to ...

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Cascade Mode The PIC in the ICH7 has one master 8259 and one slave 8259 cascaded onto the master through IRQ2. This configuration can handle separate priority levels. The master controls the slaves through a three ...

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Functional Description 5.9.5 Masking Interrupts 5.9.5.1 Masking on an Individual Interrupt Request Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. ...

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Advanced Programmable Interrupt Controller (APIC) (D31:F0) In addition to the standard ISA-compatible PIC described in the previous chapter, the ICH7 incorporates the APIC. While the standard interrupt controller is intended for use in a uni-processor system, APIC can be ...

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Functional Description Table 5-16. APIC Interrupt Mapping (Sheet Via 1 IRQ # SERIRQ 16 PIRQA# 17 PIRQB# 18 PIRQC# 19 PIRQD# 20 N/A 21 N/A 22 N/A 23 N/A NOTES: 1. When programming the polarity of internal ...

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Edge-Triggered Operation In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt. 5.10.4.2 Level-Triggered Operation In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt. ...

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Functional Description Table 5-18. Interrupt Message Data Format Bit 31:16 Will always be 0000h. Trigger Mode Level Edge. Same as the corresponding bit in the I/O 15 Redirection Table for that interrupt. Delivery Status ...

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The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In this mode, the ICH7 asserts the start frame. This start frame PCI clocks wide based upon the Serial ...

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Functional Description 5.11.5 Data Frame Format Table 5-20 shows the format of the data frames. For the PCI interrupts (A output from the ICH7 is ANDed with the PCI input signal. This way, the interrupt can be signaled via both ...

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Real Time Clock (D31:F0) The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for general purpose ...

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Functional Description 5.12.2 Interrupts The real-time clock interrupt is internally routed within the ICH7 both to the I/O APIC and the 8259 mapped to interrupt vector 8. This interrupt does not leave the ICH7, nor is it shared ...

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Table 5-21. Configuration Bits Reset by RTCRST# Assertion (Sheet Bit Name Alarm Interrupt Enable (AIE) Alarm Flag (AF) SWSMI_RATE_SEL SLP_S4# Minimum Assertion Width SLP_S4# Assertion Stretch Enable RTC Power Status (RTC_PWR_STS) Power Failure (PWR_FLR) AFTERG3_EN Power Button ...

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Functional Description Table 5-21. Configuration Bits Reset by RTCRST# Assertion (Sheet Bit Name NEWCENTURY_STS Intruder Detect (INTRD_DET) Top Swap (TS) PATA Reset State (PRS) (Mobile/Ultra Mobile Only) Using a GPI to Clear CMOS A jumper on a ...

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INIT# (Initialization) The INIT# signal is active (driven low) based on any one of several events described in Table 5-22. When any of these events occur, INIT# is driven low for 16 PCI clocks, then driven high. Note: The ...

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Functional Description Figure 5-7. Coprocessor Error Timing Diagram FERR# Internal IRQ13 I/O Write to F0h IGNNE# If COPROC_ERR_EN is not set, the assertion of FERR# will have not generate an internal IRQ13, nor will the write to F0h generate IGNNE#. ...

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Dual-Processor Issues (Desktop Only) 5.13.2.1 Signal Differences In dual-processor designs, some of the processor signals are unused or used differently than for uniprocessor designs. Table 5-24. DP Signal Differences Signal A20M# / A20GATE STPCLK# FERR# / IGNNE# 5.13.2.2 Power ...

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Functional Description 5.14 Power Management (D31:F0) 5.14.1 Features • Support for Advanced Configuration and Power Interface, Version 2.0 (ACPI) providing power and thermal management — ACPI 24-Bit Timer — Software initiated throttling of processor performance for Thermal and Power Reduction ...

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Table 5-25. General Power States for Systems Using Intel State/ Substates Stop-Clock: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant cycle, halts its instruction stream. ICH7 then asserts G0/S0/C3 DPSLP# followed by STP_CPU#, which forces ...

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Functional Description Table 5-26. State Transition Rules for Intel Present State • Processor halt instruction • Level 2 Read • Level 3 Read (Mobile Only) G0/S0/C0 • Level 4 Read (Mobile Only) • SLP_EN bit set • Power Button Override ...

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System Power Planes The system has several independent power planes, as described in that when a particular power plane is shut off, it should level. s Table 5-27. System Power Plane Controlled Plane SLP_S3# ...

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Functional Description In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The interrupt polarity changes depending on whether interrupt shareable with a PIRQ or not ...

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Table 5-28. Causes of SMI# and SCI (Sheet 1-5 Cause TCO SMI — NMI occurred (and NMIs mapped to SMI) TCO SMI — INTRUDER# signal goes active TCO SMI — Change of the BIOSWP bit from 0 ...

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Functional Description 5.14.4.1 PCI Express* SCI (Desktop and Mobile Only) PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using messages. When a PME message is received, the ICH7 will set the PCI_EXP_STS bit. If ...

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Table 5-29. Break Events (Mobile/Ultra Mobile Only) Event Any unmasked interrupt goes active Any internal event that cause an NMI or SMI# Any internal event that cause INIT active Any bus master request (internal, external or DMA, or ...

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Functional Description 5.14.5.2 Deferred C3/C4 (Mobile/Ultra Mobile Only) Due to the new DMI protocol, if there is any bus master activity (other than true isoch), then the C0-to-C3 transition will pause at the C2 state. ICH7 will keep the processor ...

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Conditions for Checking the PCI Clock When there is a lack of PCI activity the ICH7 has the capability to stop the PCI clocks to conserve power. “PCI activity” is defined as any activity that would require the PCI ...

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Functional Description 5.14.7 Sleep States 5.14.7.1 Sleep State Overview The ICH7 directly supports different sleep states (S1–S5) that are entered by setting the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based ...

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Table 5-31. Causes of Wake Events Cause RTC Alarm Power Button GPI[0:15] Classic USB LAN (Desktop and Mobile only) RI# ® AC ‘97 / Intel High Definition Audio Primary PME# Secondary PME# PCI_EXP_WAKE# (Desktop and Mobile only) PCI_EXP PME Message ...

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Functional Description It is important to understand that the various GPIs have different levels of functionality when used as wake events. The GPIs that reside in the core power well can only generate wake events from sleep states where the ...

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Table 5-33. Transitions Due to Power Failure State at Power Failure S0, S1 5.14.8 Thermal Management The ICH7 has mechanisms to assist with managing thermal problems in the system. 5.14.8.1 THRM# Signal The THRM# signal is used ...

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Functional Description 5.14.8.3 THRM# Override Software Bit The FORCE_THTL bit allows the BIOS to force passive cooling, independent of the ACPI software (which uses the THTL_EN and THTL_DTY bits). If this bit is set, the ICH7 starts throttling using the ...

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Power Button Override Function If PWRBTN# is observed active for at least four consecutive seconds, the state machine should unconditionally transition to the G2/S5 state, regardless of present state (S0– S4), even if PWROK is not active. In this case, ...

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Functional Description 5.14.9.3 PME# (PCI Power Management Event) The PME# signal comes from a PCI device to request that the system be restarted. The PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when ...

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During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, VRMPWRGD/VGATE, and PLTRST# are all ‘1’. During entry into a powered-down state (due to S3, S4, S5 entry, power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3 PWROK ...

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Functional Description 5.14.10.1 Write Only Registers with Read Paths in ALT Access Mode The registers described in number field in the table indicates which register will be returned per access to that port. Table 5-36. Write Only Registers with Read ...

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Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet Restore Data I Access Addr Rds 1 DMA Chan 0–3 Command 2 DMA Chan 0–3 Request DMA Chan 0 Mode: 3 Bits(1:0) ...

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Functional Description 5.14.10.2 PIC Reserved Bits Many bits within the PIC are reserved, and must have certain values written in order for the PIC to operate properly. Therefore, there is no need to return these values in ALT access mode. ...

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Cutting power to the core may be done via the power supply external FETs to the motherboard. The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core supply, as well as power ...

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Functional Description 5.14.11.4 CPUPWRGD Signal This signal is connected to the processor’s VRM via the VRMPWRGD signal and is internally AND’d with the PWROK signal that comes from the system power supply. 5.14.11.5 VRMPWRGD Signal VRMPWRGD is an input from ...

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Clock Generators The clock generator is expected to provide the frequencies shown in ® Table 5-39. Intel ICH7 Clock Inputs Clock Frequency Domain SATA_CLK 100 MHz (Desktop and Differential Mobile Only) 100 MHz DMI_CLK Differential PCICLK 33 MHz 48.000 ...

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Functional Description 5.14.13 Legacy Power Management Theory of Operation Instead of relying on ACPI software, legacy power management uses BIOS and various hardware mechanisms. The scheme relies on the concept of detecting when individual subsystems are idle, detecting when the ...

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System Management (D31:F0) The ICH7 provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. In addition, ICH7 provides integrated ASF Management support. Features and functions can ...

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Functional Description If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written then the INTRD_DET signal will when INTRUDER# input signal goes inactive. Note that this is slightly different ...

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The following rules/steps apply if the system state and the policy is for the ICH7 to reboot the system after a hardware lockup detecting the lockup, the SECOND_TO_STS bit is set. The ICH7 may ...

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Functional Description 5. After step 4 (power button override), if the user presses the power button again, the system should wake state and the processor should start executing the BIOS step 5 (power button press) ...

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Note: Notes for previous two numbered lists. 1. Normally, the ICH7 does not send heartbeat messages while in the G0 state (except in the case of a lockup). However hardware event (or heartbeat) occurs just as the system ...

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Functional Description Table 5-40. Heartbeat Message Data (Sheet Field SEQ[3:0] System Power State MESSAGE1 MESSAGE2 WDSTATUS 5.16 IDE Controller (D31:F1) The ICH7 IDE controller features one sets of interface signals that can be enabled, tri- stated or ...

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PIO IDE Timing Modes IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency. Startup latency is incurred when a PCI master cycle targeting the IDE data port is decoded and the DA[2:0] and CSxx# ...

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Functional Description 5.16.1.4 PIO IDE Data Port Prefetching and Posting The ICH7 can be programmed via the IDETIM registers to allow data to be posted to and prefetched from the IDE data ports. Data prefetching is initiated when a data ...

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Figure 5-8. Physical Region Descriptor Table Entry Byte 3 Memory Region Physical Base Address [31:1] EOT Reserved 5.16.2.2 Bus Master IDE Timings The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The DMA ...

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Functional Description 5.16.2.4 Bus Master IDE Operation To initiate a bus master transfer between memory and an IDE device, the following steps are required: 1. Software prepares a PRD table in system memory. The PRD table must be DWord- aligned ...

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Table 5-42. Interrupt/Active Bit Interaction Definition Interrupt Active 5.16.2.5 Error Conditions IDE devices are sector based mass storage devices. The drivers handle errors on a sector basis; either a sector is transferred ...

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Functional Description 5.16.3.1 Operation Initial setup programming consists of enabling and performing the proper configuration of the ICH7 and the IDE device for Ultra ATA/100/66/33 operation. For the ICH7, this consists of enabling synchronous DMA mode and setting up appropriate ...

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Ultra ATA/33/66/100 Timing The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA Timing register and the IDE Configuration register. Different timings can be programmed for each drive in the system. The Base Clock frequency for each ...

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Functional Description 5.17 SATA Host Controller (D31:F2) (Desktop and Mobile Only) The SATA function in the ICH7 has dual modes of operation to support different operating system conditions. In the case of Native IDE enabled operating systems, the ICH7 has ...

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Table 5-44. SATA Feature Description Feature Native Command Queing (NCQ) Auto Activate for DMA Hot Plug Support Asynchronous Signal Recovery 3 Gb/s Transfer Rate ATAPI Asynchronous Notification Host Initiated Power Management Staggered Spin-Up Command Completion Coalescing Port Multiplier External SATA ...

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Functional Description If software clears bit 7 of the control register before performing a read, the last item written will be returned from the FIFO. If software sets bit 7 of the control register before performing a read, the first ...

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Intel Matrix Storage Manager RAID Option ROM The Intel Matrix Storage Manager RAID Option ROM is a standard PnP Option ROM that is easily integrated into any System BIOS. When in place, it provides the following three primary ...

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Functional Description Figure 5-9. SATA Power States PHY = Ready 5.17.4.2 Power State Transitions 5.17.4.2.1 Partial and Slumber State Entry/Exit The partial and slumber states save interface power when the interface is idle. It would be most analogous to PCI ...

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Non-AHCI Mode PME# Generation When in non-AHCI mode (legacy mode) of operation, the SATA controller does not generate PME#. This includes attach events (since the port must be disabled), or interlock switch events (via the SATAGP pins). 5.17.4.3 SMI ...

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Functional Description 5.17.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) The 100 MHz Serial ATA Reference Clock (SATACLKP, SATACLKN) is implemented on the system as a ground-terminated low-voltage differential signal pair driven by the system Clock Chip. When all ...

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The main counter is clocked by the 14.31818 MHz clock, synchronized into the 66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. The accuracy of the main counter ...

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Functional Description The Timer 0 Comparator Value register cannot be programmed reliably by a single 64- bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. If the actual Timer 0 Comparator Value ...

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Issues Related to 64-Bit Timers with 32-Bit Processors A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit instructions. However, a 32-bit processor may not be able to directly read 64-bit timer. A ...

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