GC80960RP3V33 Intel Corporation, GC80960RP3V33 Datasheet
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Intel i960 RX I/O Processor at 3.3 Volts Datasheet • 33 MHz, 3.3 Volt Version (80960RP 33/3.3) • 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core • Complies with PCI Local Bus Specification, Revision ...
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... OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. ...
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Contents 1.0 About This Document ................................................................................................................... 7 ® 1.1 Intel Solutions960 1.2 Terminology .......................................................................................................................... 7 1.3 Additional Information Sources ............................................................................................. 8 2.0 Functional Overview ..................................................................................................................... 9 2.1 Key Functional Units ........................................................................................................... 10 2.1.1 PCI-to-PCI Bridge Unit........................................................................................... 10 2.1.2 Private PCI ...
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Intel i960 RX I/O Processor at 3.3 Volts Contents 4.4.4 APIC Bus Interface Signal Timings........................................................................ 53 2 4.4 Interface Signal Timings .................................................................................. 54 4.5 AC Test Conditions............................................................................................................. 55 4.6 AC Timing Waveforms........................................................................................................ 55 4.7 Memory Controller ...
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Figures 1 Product Name Functional Block Diagram..................................................................................... 9 2 80960JF Core Block Diagram..................................................................................................... 12 3 352L HL-PBGA Package Diagram (Top and Side View)............................................................ 30 4 352L HL-PBGA Package Diagram (Bottom View)...................................................................... 31 5 Thermocouple Attachment - No Heat Sink ................................................................................. ...
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Intel i960 RX I/O Processor at 3.3 Volts Contents Tables 1 Related Documentation ................................................................................................................ 8 2 80960RX Instruction Set............................................................................................................. 16 3 Signal Type Definition................................................................................................................. 17 4 Signal Descriptions ..................................................................................................................... 18 5 Power Requirement, Processor Control and Test Signal ...
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About This Document This is the data sheet for the low-power (3.3 V) versions of the Intel Processor family (80960RX), including: ® • Intel 80960RD 66/3.3 (80960RD) ® • Intel 80960RP 33/3.3 (80960RP) Throughout this document, these family members ...
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Intel i960 RX I/O Processor at 3.3 Volts About This Document 1.3 Additional Information Sources Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales. 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Table ...
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Functional Overview As indicated in Figure 1 an intelligent I/O processor. Subsections following the figure briefly describe the main features; for detailed functional descriptions, refer to the Intel User’s Guide (272736). The PCI bus is an industry standard, high ...
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Intel i960 RX I/O Processor at 3.3 Volts Functional Overview 2.1 Key Functional Units 2.1.1 PCI-to-PCI Bridge Unit The PCI-to-PCI bridge unit (referred to as “bridge”) connects two independent PCI buses fully compliant with the PCI-to-PCI ...
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Memory Controller The Memory Controller allows direct control of external memory systems, including DRAM, SRAM, ROM and Flash Memory. It provides a direct connect interface to memory that typically does not require external logic. It features programmable chip selects, ...
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Intel i960 RX I/O Processor at 3.3 Volts Functional Overview ® ® 2.2 Intel i960 The processing power of the 80960RX comes from the 80960JF processor core. The 80960JF is a new, scalar implementation of the 80960 Core ...
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Burst Bus A 32-bit high-performance bus controller interfaces the 80960RX to external memory and peripherals. The Bus Control Unit fetches instructions and transfers data on the local bus at the rate four 32-bit words per six ...
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Intel i960 RX I/O Processor at 3.3 Volts Functional Overview 2.2.4 Faults and Debugging The 80960RX employs a comprehensive fault model. The processor responds to faults by making implicit calls to a fault handling routine. Specific information collected ...
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Memory-Mapped Control Registers The 80960RX is compliant with 80960 family architecture and has the added advantage of memory-mapped, internal control registers not found on the 80960KX, 80960SX or 80960CX processors. This feature provides software an interface to easily read ...
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Intel i960 RX I/O Processor at 3.3 Volts Functional Overview Table 2. 80960RX Instruction Set Data Movement Load Store Move Conditional Select Load Address Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check ...
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Package Information 3.1 Package Introduction The 80960RX is offered in a SuperBGA* Ball Grid Array (HL-PBGA) package. This is a perimeter array package with four rows of ball connections in the outer area of the package. See Figure 4, ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 4. Signal Descriptions (Sheet Name AD31:0 ADS# ALE BLAST# 18 Type ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit ...
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Table 4. Signal Descriptions (Sheet Name BE3:0# DEN# D/C#/ RST_MODE# DT/R# Datasheet ® Intel Type BYTE ENABLES select which four data bytes on the bus participate in the current bus access. Byte enable encoding ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 4. Signal Descriptions (Sheet Name LOCK#/ONCE# LRDYRCV# HOLD HOLDA RDYRCV# 20 Type BUS LOCK indicates that an atomic read-modify-write operation is in progress. The ...
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Table 4. Signal Descriptions (Sheet Name W/R# WIDTH/ HLTD0 WIDTH/ HLTD1/ RETRY Datasheet ® Intel Type WRITE/READ specifies during a O read latched on-chip and remains valid during T R(0) H( Read P(Q) ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 5. Power Requirement, Processor Control and Test Signal Descriptions Name Type O R(0) FAIL# H(Q) L_RST STEST S(L) TCK I I TDI S(L) O R(Q) ...
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Table 6. Interrupt Unit Signal Descriptions Name Type NMI# A(L) S_INT[A:D]#/ XINT3:0# A(L) XINT7:4# A(L) NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, Revision 2.1 for a more complete definition. ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 7. PCI Signal Descriptions (Sheet Name P_AD31:0 P_C/BE3:0# P_DEVSEL# P_FRAME# P_GNT# P_IDSEL P_INT[A:D]# P_IRDY# P_LOCK# P_PAR P_PERR# P_REQ# P_RST# P_SERR# NOTE: 1. PCI signal ...
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Table 7. PCI Signal Descriptions (Sheet Name P_STOP# P_TRDY# S_AD31:0 S_C/BE3:0# S_DEVSEL# S_FRAME# S_GNT0#/ S_REQ# S_GNT5:1# S_IDSEL S_IRDY# S_LOCK# S_PAR S_PERR# S_REQ0#/ S_GNT# S_RST# NOTE: 1. PCI signal functions are summarized in this data sheet; refer to ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 7. PCI Signal Descriptions (Sheet Name S_SERR# S_STOP# S_TRDY# S_REQ4:1# S_REQ5#/ S_ARB_EN NOTE: 1. PCI signal functions are summarized in this data sheet; refer ...
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Table 8. Memory Controller Signal Descriptions (Sheet Name Type R(1) CAS7:0# H(Q) P(Q) R(1) CE1:0# H(Q) P(Q) R(0) DALE1:0 H(Q) P(Q) R(X) DP3:0 H(Q) P(Q) R(1) DWE1:0# H(Q) P(Q) R(1) LEAF1:0# H(Q) P(Q) Datasheet Intel COLUMN ADDRESS ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 8. Memory Controller Signal Descriptions (Sheet Name Type R(X) MA11:0 H(Q) P(Q) R(1) MWE3:0# H(Q) P(Q) R(1) RAS3:0# H(Q) P(Q) 28 MULTIPLEXED ADDRESS signals ...
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Table 9. DMA, APIC Units Signal Descriptions Name Type O R(1) DACK# H(Q) P(Q) I DREQ# S(L) PICCLK I I/O OD PICD1:0 R(Z) H(Q) P(Q) I/O OD SCL R(Z) H(Q) P(Q) I/O OD SDA R(Z) H(Q) P(Q) ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information 3.1.2 352-Lead HL-PBGA Package Figure 3. 352L HL-PBGA Package Diagram (Top and Side View) Ball A1 Corner 1.63 mm 0.63 ± 0.07 mm 1.54 ± 0.13 mm NOTES: ...
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Figure 4. 352L HL-PBGA Package Diagram (Bottom View Datasheet ® ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet Signal AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 ...
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Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet Signal P_AD7 P_AD8 P_AD9 P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 P_C/BE0# ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet Signal S_RST# S_SERR# S_STOP# S_TRDY# SCL SDA STEST TCK TDI TDO TMS TRST ...
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Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet Signal W/R# WAIT# Datasheet ® Intel i960 Ball # Signal Ball # W4 WIDTH/HLTD0 AF5 Y23 WIDTH/HLTD1/RETRY AE5 C22 XINT4 XINT5# ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet Ball # Signal CCPLL3 A5 MA6 A6 ...
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Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet Ball # Signal F3 RAS3 F23 V F24 S_REQ3# F25 S_CLK F26 S_GNT3# G1 CAS3# G2 CAS4# G3 CAS2 G23 V G24 S_GNT1# ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet Ball # Signal Y23 V Y24 S_AD10 Y25 S_AD12 Y26 S_AD11 AA1 ICEBRK# AA2 ICEMSG# ...
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Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet Ball # Signal AF17 P_PERR# AF18 P_C/BE1# AF19 P_AD13 AF20 P_AD10 Datasheet ® ® Intel i960 RX I/O Processor at 3.3 Volts Ball # Signal Ball # ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information 3.2 Package Thermal Specifications The device is specified for operation when T 0° 95° C. Case temperature may be measured in any environment to determine whether ...
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Figure 6. Thermocouple Attachment - With Heat Sink 3.2.1.3 Thermal Resistance The thermal resistance value for the case-to-ambient, cooling solution thermal performance. Datasheet ® ® Intel i960 Thermocouple 3.8 mm Diameter Hole CA RX I/O Processor at 3.3 Volts Package ...
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Intel i960 RX I/O Processor at 3.3 Volts Package Information 3.2.2 Thermal Analysis This thermal analysis is based on the following assumptions: • Power dissipation is a constant 5 W. • Maximum case temperature is 95° C. Table ...
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Sources for Heatsinks and Accessories The following is a list of suggested sources for heatsinks and accessories. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. Table 15. Heat ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 4.0 Electrical Specifictions 4.1 Absolute Maximum Ratings Parameter Storage Temperature Case Temperature Under Bias Supply Voltage wrt. V Supply Voltage wrt. V Voltage on Any Ball wrt. V ...
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V Pin Requirements (V CC5 In mixed voltage systems that drive 80960RX processor inputs in excess of 3.3 V, the V pin must be connected to the system 5 V supply. To limit current flow into the V CC5 ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 4.3 Targeted DC Specifications Table 18. DC Characteristics Symbol V Input Low Voltage IL Input High Voltage for all signals V IH1 except SCLK V Input High Voltage ...
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Table 19. I Characteristics CC Symbol Input Leakage Current for each signal except PCI Bus Signals, LOCK#/ONCE#, I WIDTH/HLTD0, WIDTH/HLTD1/RETRY, LI1 BLAST#, D/C#/RST_MODE#, DEN#,TMS, TRST#, TDI Input Leakage Current for LOCK#/ONCE#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, I LI2 BLAST#, D/C#/RST_MODE#, DEN#, TMS, TRST#, ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 4.4 Targeted AC Specifications Table 20. Input Clock Timings Symbol T S_CLK Frequency F T S_CLK Period C T S_CLK Period Stability CS T S_CLK High Time CH ...
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Table 22. Synchronous Input Timings Sym Input Setup to S_CLK — NMI#, XINT7:4#, T IS1 S_INT[A:D]#/XINT3:0#, DP3:0# Input Setup to S_CLK — for all accesses except Expansion ROM T IS1A Accesses — AD31:0 only Input Setup to S_CLK during Expansion ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 4.4.1 Relative Output Timings Table 23. Relative Output Timings Symbol T ALE Width LXL T Address Hold from ALE Inactive LXA T DT/R# Valid to DEN# Active DXD ...
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Table 25. Fast Page Mode Interleaved DRAM Output Timings (Sheet Symbol T DALE1:0 Burst Falling Edge Output Valid Delay OV19 T DALE1:0 Rising Edge Output Valid Delay OV20 LEAF1:0# Rising and Falling Edge Output Valid T OV21 ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions Table 27. BEDO DRAM Output Timings (Sheet MA11:0 Output Valid Delay - Column Address Write Cycles OV38 T DWE1:0# Rising and Falling Edge Output ...
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Table 29. Boundary Scan Test Signal Timings (Sheet Symbol All Outputs (Non-Test) Float T BSOF2 Delay Input Setup to TCK — All T BSIS2 Inputs (Non-Test) Input Hold from TCK — All T BSIH2 Inputs (Non-Test) NOTES: ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 2 4.4 Interface Signal Timings 2 Table 31 Interface Signal Timings Symbol F SCL Clock Frequency SCL T Bus Free Time Between STOP and ...
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AC Test Conditions The AC Specifications in with the 50 pF load indicated in Figure 8. AC Test Load 4.6 AC Timing Waveforms Figure 9. S_CLK, TCLK Waveform T Figure 10. T Output Delay Waveform OV S_CLK Datasheet Intel ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions Figure 11. T Output Float Waveform OF S_CLK Figure 12. T and T Input Setup and Hold Waveform IS IH S_CLK 56 1.5V 1. 1.5V 1.5V ...
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Figure 13. T and T Relative Timings Waveform LXL LXA Figure 14. DT/R# and DEN# Timings Waveform S_CLK DT/R# DEN# Datasheet ® Intel T A 1.5V S_CLK T LXL ALE Valid 1.5V T LXA AD31:0 1.5V Valid T A 1.5V ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 2 Figure 15 Interface Signal Timings SDA T BUF SCL Stop Start 58 T LOW HDSTA HDDAT ...
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Memory Controller Output Timing Waveforms Figure 16. Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus S_CLK AD31:0 MA11:0 ALE ADS# W/R# BLAST# DT/R# DEN# DWE0# RAS0# CAS3:0# LRDYRCV# RDYRCV# Datasheet ® Intel i960 T T ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions Figure 17. Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus S_CLK AD31:0 MA11:0 ALE ADS# BE3:0# W/R# BLAST# DT/R# MWE0# DWE0# RAS0# CAS3:0# LRDYRCV# ...
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Figure 18. FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States S_CLK AD[31:0] RAS[n]# RAS[n+1#] MA[11:0] DALE[0]# CAS[3:0]# LEAF[0]# DALE[1]# CAS[7:4]# LEAF[1]# DWE[1:0]# Datasheet ® ® Intel i960 RX I/O Processor at 3.3 Volts ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions Figure 19. FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States S_CLK AD[31:0] RAS[n]# RAS[n+1]# MA[11:0] DALE[0]# CAS[3:0]# LEAF[0]# DALE[1]# CAS[7:4]# LEAF[1]# DWE[1:0 ...
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Figure 20. EDO DRAM, Read Cycle S_CLK RAS# MA[11:0] CAS# AD[31:0] Figure 21. EDO DRAM, Write Cycle MA[11:0] AD[31:0] Datasheet Intel COL ROW COL D ADDR ...
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Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions Figure 22. BEDO DRAM, Read Cycle S_CLK RAS# MA[11:0] CAS# AD[31:0] Figure 23. BEDO DRAM, Write Cycle MA[11:0] RITE CAS COL COL ...
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Figure 24. 32-Bit Bus, SRAM Read Accesses with 0 Wait States MA[11:0] MWE[3:0]# AD[31:0] Figure 25. 32-Bit Bus, SRAM Write Accesses with 0 Wait States MWE[3:0]# Datasheet Intel S_CLK CE[1]# ADDR ADDR ...
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Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS 5.0 BUS FUNCTIONAL WAVEFORMS Figure 26. Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# ...
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Figure 27. Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Datasheet ® Intel i960 BUS FUNCTIONAL WAVEFORMS ...
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Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS Figure 28. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# 68 ...
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Figure 29. Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE1/A1# BE0/A0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Datasheet ® Intel i960 BUS FUNCTIONAL WAVEFORMS ...
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Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS Figure 30. Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read, 16-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE1/A1# ...
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Figure 31. Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Datasheet ® Intel i960 T ...
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Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS Figure 32. HOLD/HOLDA Waveform For Bus Arbitration S_CLK Outputs: AD31:0, ALE, ADS#, BE3:0# D/C#/RSTMODE# LRDYRCV#, FAIL# WIDTH/HLTD1, WIDTH/HLTD1/RETRY, W/R#, DT/R#, DEN#, BLAST#, LOCK#/ONCE# HOLD HOLDA NOTE: HOLD ...
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Figure 33. 80960 Core Cold Reset Waveform S_CLK V CC ADS#, BE3:0# BLAST#, DEN# LRDYRCV ALE, DT/R#, HOLD, HOLDA, W/R# FAIL# AD31:0 P_RST# D/C#/RST_MODE#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY LOCK#/ ONCE# STEST 1 ms power and clock stable NOTES: 1. The processor asserts ...
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Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS Figure 34. 80960 Local Bus Warm Reset Waveform S_CLK ADS#, BE3:0#,DEN#, BLAST#, D/C#/RST_MODE#, LRDYRCV#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, ALE, W/R#,DT/R# FAIL# AD31:0 HOLD HOLDA LOCK#/ONCE# STEST S_RST#, P_RST# L_RST# ...
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... V Product Type - Indicates the generation or “family member”. Generation Type - Indicates the generation of the device. Model Type - Indicates member within a series and specific model information. Manufacturer ID - Indicates manufacturer ID assigned by IEEE. 0000 0001 001 = Intel Corporation Constant ® ® i960 RX I/O Processor at 3.3 Volts DEVICE IDENTIFICATION ON RESET ® ...
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Intel i960 RX I/O Processor at 3.3 Volts DEVICE IDENTIFICATION ON RESET This page intentionally left blank. 76 Datasheet ...