SK70704PE Intel Corporation, SK70704PE Datasheet

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SK70704PE

Manufacturer Part Number
SK70704PE
Description
Communications: 784Kbps HDSL Data Pump Chip Set
Manufacturer
Intel Corporation
Datasheet

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SK70704/SK70707 or SK70708
1168 Kbps HSDL Data Pump Chip Set
The HDSL Data Pump is a chip set consisting of the following two devices:
The HDSL Data Pump is a 2-wire transceiver which provides echo-cancelling and 2B1Q line
coding. It incorporates transmit pulse shaping, filtering, line drivers, receive equalization, timing
and data recovery to provide 1168 kbps, clear-channel, “data pipe” transmission. The Data Pump
provides Near-End Cross-Talk (NEXT) performance in excess of that required over all ETSI test
loops. Typical transmission range on 0.4 mm cable exceeds 3.6 km in a noise-free environment
or 2.8 km with a 0 dB margin over 10 V/ Hz ETSI noise.
The Data Pump meets the requirements of
HDSL transmission system from the twisted pair interface back to the Data Pump/HDSL data
interface. The Data Pump can be used at either the NTU or the LTU end of the interface.
Applications
Product Features
As of January 15, 2001, this document replaces the Level One document
SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set.
SK70704 Analog Core Chip (ACC)
SK70707 (68-pin PLCC) or SK70708 (44-pin PLCC) HDSL Digital Transceiver (HDX)
E1 (2-pair) and fractional E1 transport
N-channel digital pair-gain
Wireless base station to switch interface
Fully integrated, 2-chip set for interfacing
to 2-wire HDSL lines at 1168 kbps
Single +5 V supply
Integrated line drivers, filters and hybrid
circuits result in greatly reduced external
logic and simplified support circuitry
requirements
Simple line interface circuitry, via
transformer coupling, to twisted pair line
Internal ACC voltage reference
Integrated VCO circuitry
Converts serial binary data to scrambled
2B1Q
encoded data
Self-contained activation/start-up state
machine for simplified single loop designs
ETSI ETR-152
Campus and private networking
High-Speed digital modems
Programmable for either line termination
(LTU) or network termination (NTU)
applications
Compliant with ETSI ETR-152 (1995)
Compliant with ITU G.991.1
Design allows for operation in either
Software Control or stand alone Hardware
Control mode
Typical power consumption less than 1.2 W
allowing remote power feeding for repeater
and NTU equipment
Input or Output Reference Clock of 18.688
MHz
Digital representation of receive signal
level and noise margin values available for
SNR controlled activation
. It provides one end of a single-channel
Order Number:
Datasheet
January 2001
249193-001

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SK70704PE Summary of contents

Page 1

SK70704/SK70707 or SK70708 1168 Kbps HSDL Data Pump Chip Set The HDSL Data Pump is a chip set consisting of the following two devices: SK70704 Analog Core Chip (ACC) SK70707 (68-pin PLCC) or SK70708 (44-pin PLCC) HDSL Digital Transceiver (HDX) ...

Page 2

... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ...

Page 3

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Contents 1.0 Pin Assignments and Signal Description 2.0 Functional Description 2.1 Transmit ..............................................................................................................15 2.2 Receive ...............................................................................................................15 2.3 Control.................................................................................................................15 2.4 ACC and HDX Overview .....................................................................................15 2.4.1 Analog Core Chip (ACC) ...

Page 4

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Figures 1 SK70704/SK70707 or SK70708 Block Diagram ................................................... 7 2 Package Markings................................................................................................. 7 3 SK70704 ACC Pin Locations ................................................................................ 8 4 SK70707/SK70708 HDX Pin Assignments ........................................................... 9 5 HDX/ACC ...

Page 5

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 20 Crystal Specifications (Figure 14 21 ACC Absolute Maximum Ratings ........................................................................44 22 ACC Recommended Operating Conditions.........................................................44 23 ACC DC Electrical Characteristics (Over Recommended Range) ......................44 24 ACC Transmitter Electrical ...

Page 6

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Revision History Revision Date 6 Description Datasheet ...

Page 7

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Figure 1. SK70704/SK70707 or SK70708 Block Diagram Back CK9M TDATA TFP RDATA RFP ICLK LTU LOSW REFCLK DATA ADDR CTRL Figure 2. Package Markings Part # LOT # FPO ...

Page 8

... Identifies the Finish Process Order. 8 Figure 3 shows the ACC pin locations. Table 2 lists signal descriptions for each pin TSGN 24 DVCC 23 TVCC Rev # SK70704PE XX XXXXXX TRING 22 XXXXXXXX 21 TTIP 20 TGND 19 n Definition Table 1 lists signal Datasheet ...

Page 9

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Figure 4. SK70707/SK70708 HDX Pin Assignments n/c 10 n/c 11 n/c 12 n/c 13 ...

Page 10

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Table 1. SK70704 ACC Pin Assignments/Signal Descriptions (Continued) Group Pin # Symbol I/O 10 PGND 12 RVCC 23 TVCC Power 24 DVCC 6 DGND 15 RGND 20 TGND 3 ...

Page 11

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Table 2. SK70707/SK70708 HDX Pin Assignments/Signal Descriptions 707 708 Group Symbol Pin # Pin # 14 10 RFST 17 13 REFCLK 20 16 LTU 21 17 ICLK 49 30 ...

Page 12

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Table 2. SK70707/SK70708 HDX Pin Assignments/Signal Descriptions (Continued) 707 708 Group Symbol Pin # Pin # 4 4 QUIET 5 5 ACTREQ 6 6 reserved 7 9 ACTVNG 23 ...

Page 13

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Table 2. SK70707/SK70708 HDX Pin Assignments/Signal Descriptions (Continued) 707 708 Group Symbol Pin # Pin # 63 37 LOSWT 62 38 ILMT 61 39 RPTR Hardware Interface 64 40 ...

Page 14

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Table 2. SK70707/SK70708 HDX Pin Assignments/Signal Descriptions (Continued) 707 708 Group Symbol Pin # Pin # 18 14 CK9M 19 15 CK9MEN 32 19 CK37M 33 20 DTR Clock ...

Page 15

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 2.0 Functional Description The HDSL Data Pump is a fully-integrated, two-chip solution (see front page block diagram) which includes an SK70704 Analog Core Chip (ACC) and an SK70707/SK70708 HDSL ...

Page 16

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set The ACC provides the complete analog front end for the HDSL Data Pump. It performs transmit pulse shaping, line driving, receive A/D, and the VCO portion of the receiver ...

Page 17

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Table 3. ACC Transmit Control TSGN TMAG 2.4.3 HDX/ACC Interface The ACC provides the 37.376 MHz master clock, CK37M, to the HDX. The serial control ...

Page 18

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Table 4. HDX/ACC Serial Port Word Bit Definitions ( Figure 5) Bit Word A (on DTR TXOFF 11 TXDIS 10 TXTST 9 AGC2 8 AGC1 ...

Page 19

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 5 shows the TDATA requirements for the framer interface through the activation sequence. Once the ACTIVE Low-to-High transition occurs, the Data Pump becomes transparent. Therefore, the HDSL framer must ...

Page 20

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Figure 6. HDX/ACC Framer Interface – Relative Timing A) Transmit Timing - Without Stuff Bits ICLK TFP TDATA b7003 B) Transmit Timing - With Stuff Bits ICLK TFP TDATA ...

Page 21

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Figure 7. Model for HDSL Data Pump and HDSL Framer Applications NTU TDATA LXP710 TFP HDSL LOSW To E1 I/F Framer - ICLK (E1-R) R RDATA RFP RPOS RFST ...

Page 22

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Data Write: The Data Write pin (WRITE) requires an active Low pulse to enable a write transfer on the data bus. Data transfer is triggered by the rising edge ...

Page 23

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 2.7.3 Registers Three write registers and seven read registers are available to the user. and the following paragraphs describe them in more detail. Some of the registers contain reserved ...

Page 24

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Table 7. Main Control Register WR0 (Continued) Bit b3 reserved. This bit must be set to 0. Insertion Loss Measurement Test (ILMT). Set ILMT enable transmission ...

Page 25

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Table 9. Read Coefficient Select Register WR3 Hex Value 00-07 08-0F 10-15 16-19 1A 1B-FF 2.7.3.4 RD0—Main Status Register Address: A3-0 = 0000 Default: xxh (x=undefined) Attribute: Read Only ...

Page 26

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set The 8-bit word in this register is the eight most significant bits of the main FFE AGC tap, which, along with the AGC and DAGC values (RD6), represent the ...

Page 27

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Table 12. Noise Margin Register RD2 (Continued) Noise Margin Coding MSB ...

Page 28

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Table 13. Coefficient Read Register Bit b7-b0 Coefficient Word Value. RD3 contains the lower byte; RD4 the upper byte. 2.7.3.8 RD5—Activation Status Register Address: A3-0 = 0101 Default: xxh ...

Page 29

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Table 15. Receiver AGC and FFE Step Gain Register RD6 Bit b7 Data Pump Activation State–bit 2 (ST2). b6 Data Pump Activation State–bit 1 (ST1). Digital Gain Word–bit 1 ...

Page 30

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set During the Activating State, the echo canceller, equalizer and timing recovery circuits are all adapting during the simultaneous transmission and reception of the framed, scrambled-ones data transmitted as a ...

Page 31

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Table 16. Data Pump/Framer Activation State Machine Correspondences (Continued) ST2 ST1 ST0 The data pump samples ...

Page 32

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Figure 8. LTU Data Pump Activation State Machine LOSWT 0 1 Pending De-Activation Txmitting 2B1Q Data ( LOSW 1 0 Active 2 Txmitting 2B1Q Live data (0, ...

Page 33

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 2.8.3 NTU Data Pump Activation Figure 10 and Figure 11 HDSL Framer State Machine. The activation state machines for NTU and LTU devices are similar. Both Data Pump machines ...

Page 34

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Table 17. Activation – Synchronization Activation State Activating Active Pending De-Activation Figure 10. NTU Data Pump Activation State Machine LOSWT 0 Pending De-Activation Txmitting 2B1Q Data ( ...

Page 35

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Figure 11. NTU HDSL Framer Activation State Machine Idle LOSWT = 1 Datasheet ACTIVE & indc Active-T ACTIVE & INDR Active-R ...

Page 36

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Figure 12. HDSL Synchronization State Machine No Sync Initial "Out-of-Sync" State 0 ACTIVE = 0 LOSW = 0 LOS = 1 LOS = 1 or LOSWT = 1 Out ...

Page 37

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 3.0 Application Information 3.1 HDSL Framer State Machine Design There are two issues that impact implementation of the HDSL Framer Activation State machines for both LTU and NTU devices. ...

Page 38

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set 3.2.2 Digital Section • Keep all digital traces separated from the analog region of the Data Pump layout • Provide high frequency decoupling capacitors (0.01 µF ceramic or monolithic) ...

Page 39

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Figure 13. PCB Layout Guidelines VCC GND ...

Page 40

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Figure 14. Typical Support Circuitry for LTU Applications + C10 [n/c] [44] [28] 9 [7] RFP TSGN 14 [10] ...

Page 41

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Table 19. Transformer Specifications (Figure 14 and Figure 15, Reference T1) Measure Turns Ratio (IC:Line) Secondary Inductance (Line Side) Leakage Inductance Interwinding Capacitance THD Longitudinal Balance Return Loss Isolation ...

Page 42

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Figure 15. Typical Support Circuitry for NTU Applications + C10 [n/c] [44] [28] 9 [7] RFP TSGN 14 [10] ...

Page 43

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Figure 16. SK70707/SK70708 HDX Control and Status Signals (Hardware Mode) NOTES: 1. This figure illustrates the HDX control and status signals in Hardware Mode. All other HDX and ACC ...

Page 44

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set 4.0 Test Specifications Note: The minimum and maximum values in represent the performance specifications of the Data Pump and are guaranteed by test, except where noted by design. Table ...

Page 45

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Table 24. ACC Transmitter Electrical Parameters (Over Recommended Range) Parameters Sym Isolated pulse height at TTIP, 1 TRING Setup time (TSGN, TMAG) t TSMSU Hold time (TSGN, TMAG) t ...

Page 46

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Figure 18. ACC Transmitter Timing A) Transmit Syntax. TCK4M TSGN TMAG B) Transmit Timing. TCK4M TSGN, TMAG Figure 19. Upper Bound of Transmit Power Spectral Density -20 -40 -60 ...

Page 47

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Figure 20. ACC Receiver Syntax and Timing A) Receive Syntax CK37M CK18M INTERNAL) FS AD0 AD1 AGCKIK Table 26. HDX Absolute Maximum Ratings Parameter 1 2 Supply voltage reference ...

Page 48

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Table 28. HDX DC Electrical Characteristics (Over Recommended Range) Parameter Supply current (full operation) Input Low voltage Input High voltage Output Low voltage Output High voltage 2 Input leakage ...

Page 49

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Figure 21. HDX/HDSL Data Interface Timing A) Non-Repeater Mode ICLK TDATA, TFP RATA, RFP, RFST B) Repeater Mode TFP ICLK TDATA RATA, RFP, RFST C) Repeater Mode REFCLK TFP ...

Page 50

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Table 30. HDX/Microprocessor Interface Timing Specifications Parameter RESET2 pulse width Low RESET2 to INT clear (10 k resistor from INT to VCC2) RESET2 to data tristate on D0-7 CHIPSEL ...

Page 51

Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 Reset and Interrupt Timing Figure 22. A) Reset Timing RESET2 INT D0-7 (Output) B) Interrupt Timing READ CHIPSEL ADDR0 - 3 INT Datasheet ( P Control Mode) t RPWL ...

Page 52

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Figure 23. Parallel Data Channel Timing A) Chip Select Timing CHIPSEL (READ = 0) D0-7 (Output) B) Data Read Timing CHIPSEL ADDR0-3 READ (WRITE = 1) D0-7 (Output) C) ...

Page 53

... Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708 5.0 Mechanical Specifications Figure 24. ACC Plastic Leaded Chip Carrier Package Specifications Analog Core Chip (ACC) • 28-pin PLCC • P/N SK70704PE (-40° 85° C) Dim BSC—Basic Spacing between Centers ...

Page 54

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set Figure 25. HDX Plastic Leaded Chip Carrier Package Specifications SK70707 HDSL Digital Transceiver (HDX) • 68-pin PLCC • ...

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