21154-AB Intel Corporation, 21154-AB Datasheet

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21154-AB

Manufacturer Part Number
21154-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21154-AB

Case
BGA
Dc
99+
21154 PCI-to-PCI Bridge
Product Features
Complies fully with the PCI Local Bus
Specification, Revision 2.1
Complies fully with the PCI Power
Management Specification, Revision 1.0
Supports 64-bit extension signals on the
primary and secondary interfaces
Implements delayed transactions for all PCI
configuration, I/O, and memory read
commands–up to three transactions
simultaneously in each direction
Allows 152 bytes of buffering (data and
address) for upstream posted memory write
commands and 88 bytes of buffering for
downstream posted memory write
commands—up to nine upstream and five
downstream posted write transactions
simultaneously
Allows 152 bytes of read data buffering
upstream and 152 bytes of read data
buffering downstream
Provides concurrent primary and secondary
bus operation to isolate traffic
Provides ten secondary clock outputs:
— Low skew, permitting direct drive of
option slots
— Individual clock disables, capable of
automatic configuration during reset
Provides arbitration support for nine
secondary bus devices:
— A programmable 2-level arbiter
— Hardware disable control, permitting use
of an external arbiter
1.
For the 21154–AB and later revisions only. The 21154–AA does not implement this feature.
Datasheet
Provides a 4-pin general-purpose I/O
interface, accessible through device-
specific configuration space
1
Provides enhanced address decoding:
— A 32-bit I/O address range
— A 32-bit memory-mapped I/O address
range
— A 64-bit prefetchable memory address
range
— ISA-aware mode for legacy support in
the first 64KB of I/O address range
— VGA addressing and VGA palette
snooping support
Includes live insertion support
Supports PCI transaction forwarding for the
following commands:
— All I/O and memory commands
— Type 1 to Type 1 configuration
commands
— Type 1 to Type 0 configuration
commands (downstream only)
— All Type 1 to special cycle configuration
commands
Includes downstream lock support
Supports both 5-V and 3.3-V signaling
environments
Available in both 33 MHz and 66 Mhz
versions
Provides an IEEE standard 1149.1 JTAG
interface
Order Number: 278108-002
July 1999

Related parts for 21154-AB

21154-AB Summary of contents

Page 1

... A programmable 2-level arbiter — Hardware disable control, permitting use of an external arbiter 1. For the 21154–AB and later revisions only. The 21154–AA does not implement this feature. Datasheet Provides a 4-pin general-purpose I/O interface, accessible through device- specific configuration space ...

Page 2

... Intel may make changes to specifications and product descriptions at any time, without notice. The 21154 PCI-to-PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...

Page 3

... Read Transactions .............................................................................................. 40 4.6.1 Prefetchable Read Transactions ............................................................ 40 4.6.2 Nonprefetchable Read Transactions...................................................... 40 4.6.3 Read Prefetch Address Boundaries ....................................................... 41 4.6.4 Delayed Read Requests ........................................................................ 41 4.6.5 Delayed Read Completion with Target................................................... 42 4.6.6 Delayed Read Completion on Initiator Bus ............................................ 42 4.7 Configuration Transaction ................................................................................... 46 4.7.1 Type 0 Access to the 21154 ................................................................... 46 4.7.2 Type 1 to Type 0 Translation..................................................................47 Datasheet 21154 PCI-to-PCI Bridge iii ...

Page 4

... Transaction Flow Through .................................................................................. 52 4.10 Transaction Termination ..................................................................................... 53 4.10.1 Master Termination Initiated by the 21154 ............................................. 54 4.10.2 Master Abort Received by the 21154 ..................................................... 54 4.10.3 Target Termination Received by the 21154 ........................................... 55 4.10.3.1Delayed Write Target Termination Response ........................... 56 4.10.3.2Posted Write Target Termination Response ............................. 56 4.10.3.3Delayed Read Target Termination Response ........................... 57 4.10.4 Target Termination Initiated by the 21154 ............................................. 59 4.10.4.1Target Retry .............................................................................. 59 4 ...

Page 5

... Exclusive Access.............................................................................................................. 87 8.1 Concurrent Locks ................................................................................................ 87 8.2 Acquiring Exclusive Access Across the 21154....................................................87 8.3 Ending Exclusive Access .................................................................................... 88 9.0 PCI Bus Arbitration........................................................................................................... 91 9.1 Primary PCI Bus Arbitration ................................................................................ 91 9.2 Secondary PCI Bus Arbitration............................................................................ 91 9.2.1 Secondary Bus Arbitration Using the Internal Arbiter ............................. 91 9.2.2 Secondary Bus Arbitration Using an External Arbiter............................. 93 9.2.3 Bus Parking ............................................................................................93 10.0 General-Purpose I/O Interface ......................................................................................... 95 10 ...

Page 6

... JTAG Signal Pins .............................................................................................. 139 16.3 Test Access Port Controller .............................................................................. 139 16.4 Instruction Register ........................................................................................... 140 16.5 Bypass Register ................................................................................................ 140 16.6 Boundary-Scan Register ................................................................................... 140 16.6.1 Boundary-Scan Register Cells ............................................................. 141 16.6.2 21154 Boundary-Scan Order ............................................................... 141 16.7 Initialization ....................................................................................................... 147 17.0 Electrical Specifications ................................................................................................. 149 17.1 PCI Electrical Specification Conformance......................................................... 149 17.2 Absolute Maximum Ratings .............................................................................. 149 17.3 DC Specifications .............................................................................................. 150 17 ...

Page 7

... PCI Signal Timing Specifications .........................................................152 17.4.3 Reset Timing Specifications ................................................................. 154 17.4.4 gpio Timing Specifications.................................................................... 154 17.4.5 JTAG Timing Specifications ................................................................. 155 18.0 Mechanical Specifications .............................................................................................. 157 Figures 1 21154 on the System Board.................................................................................. 2 2 21154 with Option Cards .......................................................................................3 3 21154 Block Diagram ............................................................................................4 4 21154 Downstream Data Path .............................................................................. 5 5 21154 PBGA Cavity Down View .........................................................................19 6 Flow-Through Posted Memory Write Transaction ...

Page 8

... Device Number to IDSEL s_ad Pin Mapping ...................................................... 48 22 21154 Response to Delayed Write Target Termination ...................................... 56 23 21154 Response to Posted Write Target Termination ........................................ 57 24 21154 Response to Delayed Read Target Termination ...................................... 57 25 Summary of Transaction Ordering ...................................................................... 72 26 Setting the Primary Interface Detected Parity Error Bit ....................................... 80 27 Setting the Secondary Interface Detected Parity Error Bit ...

Page 9

... The 21154 has sufficient clock and arbitration pins to support nine PCI bus master devices directly on its secondary interface. The 21154 allows the two PCI buses to operate concurrently. This means that a master and a target on the same PCI bus can communicate while the other PCI bus is busy. This traffic isolation may increase system performance in applications such as multimedia ...

Page 10

... Logic SCSI Option card designers can use the 21154 to implement multiple-device PCI option cards. Without a PCI-to-PCI bridge, PCI loading rules would limit option cards to one device. The PCI Local Bus Specification loading rules limit PCI option cards to a single connection per PCI signal in the option card connector ...

Page 11

... Figure 2. 21154 with Option Cards 21154 Note: 1.1 Architecture The 21154 internal architecture consists of the following major functions: • PCI interface control logic for the primary and secondary PCI interfaces • Data path and data path control logic • Configuration register and configuration control logic • ...

Page 12

... Figure 3. 21154 Block Diagram Secondary Arbiter Clocks and Reset Primary Request and Grant Table 1 describes the major functional blocks of the 21154. Table 1. 21154 Function Blocks (Sheet Function Block Primary and Secondary Control Primary-to-Secondary Data Path 4 Secondary Data Secondary Control ...

Page 13

... Read data queue To prevent deadlocks and to maintain data coherency, a set of ordering rules is imposed on the forwarding of posted and delayed transactions across the 21154. The queue structure, along with the order in which the transactions in the queues are initiated and completed, supports these ordering requirements. ...

Page 14

... The amount of read data per transaction depends on the amount of space in the queue and disconnect boundaries. Read data for up to three transactions, subject to the burst size of the read transactions and available queue space, can be stored. The read data queue for the 21154 consists of 152 bytes pointing upstream and 152 bytes pointing downstream. 6 ...

Page 15

... Signal Pins This chapter provides detailed descriptions of the 21154 signal pins, grouped by function. Table 2 describes the signal pin functional groups, and the following sections describe the signals in each group. Table 2. Signal Pin Functional Groups Function Primary PCI bus interface signal pins ...

Page 16

... During the data phases of a transaction, the initiator drives write data, or the target drives read data, on p_ad<31:0>. When the primary PCI bus is idle, the 21154 drives p_ad to a valid logic level when p_gnt_l is asserted. Primary PCI interface command/byte enables. These signals are a multiplexed command field and byte enable field ...

Page 17

... PCI transaction to complete. The 21154 samples p_lock_l as a target and can propagate the lock across to the secondary bus. The 21154 does not drive p_lock_l as an initiator; that is, the 21154 does not propagate locked transactions upstream ...

Page 18

... PCI clock cycles before asserting it again. Primary PCI bus GNT#. When asserted, p_gnt_l indicates to the 21154 that access to the primary bus is granted. The 21154 can start a transaction on the primary bus when the bus is idle and p_gnt_l is asserted. When the 21154 has not requested use of the bus and p_gnt_l is asserted, the 21154 must drive p_ad, p_cbe_l, and p_par to valid logic levels ...

Page 19

... When p_req64_l is asserted low during reset, a 64-bit data path is STS supported on the board. When p_req64_l is high during reset (indicating that a 64-bit data path is not supported on the board), the 21154 drives p_ad<63:32>, p_cbe_l<7:4>, and p_par64 to valid logic levels. When deasserting, p_req64_l is driven to a deasserted state for one cycle and then sustained by an external pull-up resistor ...

Page 20

... Devices receive data sample s_par as an input to check for possible parity errors. When the secondary PCI bus is idle, the 21154 drives s_par to a valid logic level when its secondary bus grant is asserted (one cycle after the s_ad bus is parked) ...

Page 21

... Secondary PCI interface SERR#. Signal s_serr_l can be driven low by any device except the 21154 on the secondary bus to indicate a system error condition. The 21154 samples s_serr_l as an input and I conditionally forwards it to the primary bus on p_serr_l ...

Page 22

... Signal s_req64_l has the same timing as s_frame_l. The 21154 asserts s_req64_l low during reset, indicating that a 64-bit PCI bus is supported on the board. When deasserting, s_req64_l is driven to a deasserted state for one cycle and then sustained by an external pull- up resistor ...

Page 23

... Secondary bus parking is done when s_req_l<0> is asserted, the secondary bus is idle, and the 21154 does not want to initiate a transaction. Description General-purpose I/O data ...

Page 24

... B2 power state. The 21154 disables the secondary clocks and drives them to 0. When tied low, placing the 21154 in the D3 power state has no effect on the secondary bus clocks. Primary PCI bus RST#. Signal p_rst_l forces the 21154 to a known state. ...

Page 25

... I Datasheet Description Secondary PCI bus RST#. Signal s_rst_l is driven by the 21154 and acts as the PCI reset for the secondary bus. The 21154 asserts s_rst_l when any of the following conditions is met: • Signal p_rst_l is asserted. • The secondary reset bit in the bridge control register in configuration space is set. • ...

Page 26

... Configure 66 MHz operation. This input only pin is used to specify if the 21154 is capable of running at 66 MHz. If the pin is tied high, then the device can be run at 66 MHz. If the pin is tied low, then the 21154 can only function under the 33 MHz PCI specification. ...

Page 27

... Pin Assignment This chapter describes the 21154 pin assignment and lists the pins according to location and in alphabetic order. Figure 5 shows the 21154 304-point ball grid array, representing the pins in vertical rows labeled alphabetically, and horizontal rows labeled numerically. identify pin assignments. ...

Page 28

... PCI-to-PCI Bridge 3.1 Numeric Pin Assignment Table 14 lists the 21154 pins in order of location, showing the location code, name, and signal type of each pin. Figure 5 provides the map for identifying the pin location codes, listed in alphabetic order in the PBGA Location column in ...

Page 29

... Table 14. 21154 PBGA Pin List (Sheet PBGA Location Pin Name B17 s_ad<4> B19 s_req64_l B21 vss B23 vdd C1 s_req_l<1> C3 s_ad<31> C5 s_ad<25> C7 vss C9 s_irdy_l C11 s_perr C13 s_ad<15> C15 s_ad<9> C17 s_ad<5> C19 s_cbe_l<6> C21 s_ad<60> C23 s_ad<59> D1 s_req_l<5> D3 s_req_l<3> D5 vdd D7 s_ad< ...

Page 30

... PCI-to-PCI Bridge Table 14. 21154 PBGA Pin List (Sheet PBGA Location Pin Name F23 s_ad<51> G1 s_gnt_l<4> G3 s_gnt_l<7> — G21 s_ad<47> G23 vss H1 s_gnt_l<8> H3 vss — — H21 s_ad<44> H23 s_ad<46> J1 vdd J3 vdd — — J21 vdd J23 s_ad<43> K1 s_cfn_l K3 gpio< ...

Page 31

... Table 14. 21154 PBGA Pin List (Sheet PBGA Location Pin Name P3 s_clk_o<7> — — P21 tms P23 tdi R1 vdd R3 p_rst_l — — R21 msk_in R23 vdd T1 vdd T3 p_clk — — T21 p_par64 T23 p_ad<33> U1 p_ad<29> U3 p_req_l — — U21 vss U23 p_ad< ...

Page 32

... PCI-to-PCI Bridge Table 14. 21154 PBGA Pin List (Sheet PBGA Location Pin Name Y17 p_ad<59> Y19 p_ad<52> Y21 p_ad<45> Y23 p_ad<43> AA1 p_ad<21> AA3 p_ad<20> AA5 p_frame_l AA7 p_cbe_l<1> AA9 p_ad<11> AA11 p_ad<6> AA13 p_ad<2> AA15 p_cbe_l<7> AA17 p_ad<61> ...

Page 33

... AC21 p_ad<49> AC23 vss 1. Pertains to the 21154–AB and later revisions only. For the 21154–AA, this pin is vss. 3.2 Pins Listed in Alphabetic Order Table 15 lists the 21154 pins in alphabetic order, showing the name, location code, and signal type of each pin. ...

Page 34

... PCI-to-PCI Bridge Table 15. 21154 PBGA Pin List (Sheet PBGA Pin Name Location p_ad<16> Y5 p_ad<17> AA4 p_ad<18> AB3 p_ad<19> Y4 p_ad<20> AA3 p_ad<21> AA1 p_ad<22> Y3 p_ad<23> W4 p_ad<24> W1 p_ad<25> W2 p_ad<26> V3 p_ad<27> V1 p_ad<28> V2 p_ad<29> U1 p_ad<30> U4 p_ad<31> U2 p_ad<32> T22 p_ad<33> T23 p_ad<34> U22 p_ad< ...

Page 35

... Table 15. 21154 PBGA Pin List (Sheet PBGA Pin Name Location s_ack64_l C18 s_ad<0> A18 s_ad<1> B18 s_ad<2> A17 s_ad<3> D17 s_ad<4> B17 s_ad<5> C17 s_ad<6> B16 s_ad<7> C16 s_ad<8> B15 s_ad<9> C15 s_ad<10> B14 s_ad<11> C14 s_ad<12> D13 s_ad<13> A13 s_ad< ...

Page 36

... PCI-to-PCI Bridge Table 15. 21154 PBGA Pin List (Sheet PBGA Pin Name Location s_clk J4 s_clk_o<0> L2 s_clk_o<1> L3 s_clk_o<2> M3 s_clk_o<3> M1 s_clk_o<4> M2 s_clk_o<5> N3 s_clk_o<6> N1 s_clk_o<7> P3 s_clk_o<8> P2 s_clk_o<9> P1 s_devsel_l B10 s_frame_l B9 s_gnt_l<0> E2 s_gnt_l<1> F3 s_gnt_l<2> F1 s_gnt_l<3> F2 s_gnt_l<4> G1 s_gnt_l<5> G4 s_gnt_l<6> G2 s_gnt_l<7> G3 s_gnt_l<8> H1 s_irdy_l C9 s_lock_l A11 ...

Page 37

... B2 vss B21 vss B22 vss C7 vss D8 vss D12 vss D16 vss D23 1. Pertains to the 21154–AB and later revisions only. For the 21154–AA, this pin is vss. Datasheet PBGA Type Pin Name Location P vss F4 P vss F20 P vss G23 P vss ...

Page 38

...

Page 39

... PCI transaction. The Master and Target columns indicate 21154 support for each transaction when the 21154 initiates transactions as a master, on the primary bus and on the secondary bus, and when the 21154 responds to transactions as a target, on the primary bus and on the secondary bus. ...

Page 40

... A 32-bit address uses a single address phase. This address is driven on AD<31:0>, and the bus command is driven on C/BE#<3:0>. The 21154 supports the linear increment address mode only, which is indicated when the low 2 address bits are equal either of the low 2 address bits is nonzero, the 21154 automatically disconnects the transaction after the first data transfer. 4.2.2 ...

Page 41

... FRAME# is deasserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are asserted. See transaction termination. Depending on the command type, the 21154 can support multiple data phase PCI transactions. For a detailed description of how the 21154 imposes disconnect boundaries, see description of write address boundaries and boundaries ...

Page 42

... This can occur while the 21154 is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, the 21154 asserts FRAME# and drives the stored write address out on the target bus. On the following cycle, the 21154 drives the first Dword of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received ...

Page 43

... The 21154 ends the transaction on the target bus when one of the following conditions is met: • All posted write data has been delivered to the target. • The target returns a target disconnect or target retry (the 21154 starts another transaction to deliver the rest of the write data). • ...

Page 44

... If the value in the cache line size register does meet the memory write and invalidate conditions, that is, the value is a nonzero power of 2 less than or equal to 16 Dwords, the 21154 returns a target disconnect to the initiator either on a cache line boundary or when the posted write buffer fills. For a cache line size of 16 Dwords, the 21154 disconnects a memory write and invalidate transaction on every cache line boundary ...

Page 45

... When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the 21154 claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred ...

Page 46

... Buffering Multiple Write Transactions The 21154 continues to accept posted memory write transactions as long as space for at least 8 Dwords of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, the 21154 returns a target disconnect to the initiator. ...

Page 47

... When the 21154 has posted multiple write transactions, it can initiate fast back-to-back write transactions if the fast back-to-back enable bit is set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions. The 21154 does not perform write combining or merging. ...

Page 48

... The amount of data that is prefetched depends on the type of transaction. The amount of prefetching may also be affected by the amount of free buffer space available in the 21154, and by any read address boundaries encountered. Prefetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, FIFOs, and so on. The target device’ ...

Page 49

... When the 21154 accepts a delayed read request, it first samples the read address, read bus command, and address parity. When IRDY# is asserted, the 21154 then samples the byte enable bits for the first data phase ...

Page 50

... For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The 21154 can accept 1 Dword of read data each PCI clock cycle; that is, no master wait states are inserted. The number of Dwords transferred during a delayed read transaction depends on the conditions given in disconnect is received from the target) ...

Page 51

... Datasheet CY2 CY4 CY6 CY1 CY3 CY5 CY7 Addr Addr 2 Byte Enables 2 Byte Enables Addr Data 2 Byte Enables 21154 PCI-to-PCI Bridge CY8 CY10 CY12 CY14 CY9 CY11 CY13 Addr Data 2 Byte Enables LJ-04846.AI4 43 ...

Page 52

... In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, the 21154 reflects the stalled condition to the initiator by deasserting TRDY# until more read data is available; otherwise, the 21154 does not insert any target wait states ...

Page 53

... The 21154 also conditionally asserts p_serr_l (see The 21154 has the capability to post multiple delayed read requests maximum of three in each direction initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted already contained in the delayed transaction queue ...

Page 54

... Type 0 Access to the 21154 The 21154 configuration space is accessed by a Type 0 configuration transaction on the primary interface. The 21154 configuration space cannot be accessed from the secondary bus. The 21154 responds to a Type 0 configuration transaction by asserting p_devsel_l when the following conditions are met during the address phase: • ...

Page 55

... PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. The 21154 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. The 21154 must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction ...

Page 56

... The 21154 can assert unique address lines to be used as IDSEL signals for devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted ...

Page 57

... Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the downstream direction. The 21154 initiates a special cycle on the target bus when a Type 1 configuration write transaction is detected on the initiating bus and the following conditions are met during the address phase: • ...

Page 58

... The 21154 asserts and deasserts REQ64# during the same cycles in which it asserts and deasserts FRAME#, respectively. Under certain circumstances, the 21154 does not use the 64-bit extension when initiating transactions and therefore does not assert REQ64# ...

Page 59

... Signals AD<63:32> are then unpredictable but are driven to a valid logic level. For read transactions, when the 21154 has asserted REQ64#, it drives 8 bits of byte enables on C/ BE#<7:0>. Because the only read transactions that use the 64-bit extension are prefetchable memory read transactions, the byte enable bits are always zero. Therefore, no special redirection is needed based on the target’ ...

Page 60

... Only 1 Dword of data was read from the target. When the 21154 is the target of a 64-bit memory write transaction able to accept 64 bits of data during each data phase. When the 21154 is the target of a 64-bit prefetchable memory read transaction, it supplies 64 bits of read data during each data phase and drives PAR64 corresponding to AD< ...

Page 61

... Thus, a write transaction initiated on a 32-bit, 66 MHz bus and directed to a 64-bit, 33 MHz bus can still flow-through the 21154, because the bandwidths of the two buses are the same. 4.10 Transaction Termination This section describes how the 21154 returns transaction termination conditions back to the initiator ...

Page 62

... TRDY# on the initiator bus and, for read transactions, returns FFFF FFFFh as data. When the master abort mode bit is 1, the 21154 returns target abort on the initiator bus. The 21154 also sets the signaled target abort bit in the register corresponding to the initiator bus. ...

Page 63

... When a master abort is detected in response to a posted write transaction and the master abort bit is set, the 21154 also asserts p_serr_l if enabled by the SERR# enable bit in the command register and if not disabled by the device-specific p_serr_l disable bit for master abort during posted write transactions (that is, master abort mode = 1 ...

Page 64

... The 21154 makes 2 After the 21154 makes 2 21154 asserts p_serr_l if the primary SERR# enable bit is set in the command register and the implementation-specific p_serr_l disable bit for this condition is not set in the p_serr_l event disable register. The 21154 stops initiating transactions in response to that delayed write transaction ...

Page 65

... After the 21154 makes 2 associated with that transaction, the 21154 asserts p_serr_l if the primary SERR# enable bit is set in the command register and the device-specific p_serr_l disable bit for this condition is not set in the p_serr_l event disable register. The write data is discarded. See system error conditions ...

Page 66

... PCI-to-PCI Bridge Figure 14. Delayed Read Transaction Terminated with Target Abort CY0 Cycle < 15ns > p_clk p_ad p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l 58 CY2 CY4 CY6 CY1 CY3 CY5 CY7 Addr Addr 2 Byte Enables ...

Page 67

... Target Retry The 21154 returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. The 21154 returns a target retry to an initiator when any of the following conditions is met: • For delayed write transactions: — ...

Page 68

... The 21154 is unable to obtain delayed read data from the target or to deliver delayed write data to the target after 2 When the 21154 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface attempts ...

Page 69

... If the I/O enable bit is not set, all I/O transactions initiated on the primary bus are ignored. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the master enable bit is not set, the 21154 ignores all I/O and memory transactions initiated on the secondary bus. Setting the master enable bit also allows upstream forwarding of memory transactions ...

Page 70

... The top 4 bits of the 8-bit field define bits <15:12> of the I/O base address. The bottom 4 bits read only indicate that the 21154 supports 32-bit I/O addressing. Bits <11:0> of the base address are assumed which naturally aligns the base address to a 4KB boundary. ...

Page 71

... All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of the 21154 can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary ...

Page 72

... I/O transactions. Caution: If any 21154 configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, the 21154 response to the secondary bus memory transactions is not 64 Primary Interface ...

Page 73

... Read transactions to nonprefetchable space may exhibit side effects; this space may have non-memory-like behavior. The 21154 prefetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer ...

Page 74

... Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must have no side effects. The 21154 prefetches for all types of memory read commands in this address space. ...

Page 75

... Crossing the first 4GB memory boundary If the prefetchable memory space on the secondary interface resides entirely in the first 4GB of memory, both upper 32 bits registers must be set to 0. The 21154 ignores all dual address cycle transactions initiated on the primary interface and forwards all dual address transactions initiated on the secondary interface upstream ...

Page 76

... VGA snoop mode, supporting VGA palette forwarding 5.4.1 VGA Mode When a VGA-compatible device exists downstream from the 21154, set the VGA mode bit in the bridge control register in configuration space to enable VGA mode. When the 21154 is operating in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer memory and VGA I/O registers, regardless of the values of the 21154 base and limit address registers ...

Page 77

... I/O space. Note: If both the VGA mode bit and the VGA snoop bit are set, the 21154 behaves in the same way as if only the VGA mode bit were set. ...

Page 78

...

Page 79

... Transaction Ordering To maintain data coherency and consistency, the 21154 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.1, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding across the 21154. For a more detailed discussion of transaction ordering, see Appendix E of the PCI Local Bus Specification, Revision 2 ...

Page 80

... The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a nonlocked, nonposted transaction as a master. This is true of the 21154 and must also be true of other bus agents; otherwise, a deadlock can occur. • ...

Page 81

... In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of the 21154 as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator ...

Page 82

... PCI-to-PCI Bridge The 21154 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers ...

Page 83

... If the parity error response bit is set in the bridge control register, the 21154 does not claim the transaction with s_devsel_l; this may allow the transaction to terminate in a master abort. If the parity error response bit is not set, the 21154 proceeds normally and accepts the transaction directed to or across the 21154. • ...

Page 84

... The 21154 also asserts p_perr_l. If the parity error response bit is not set, the 21154 does not assert p_perr_l. • The 21154 sets the detected parity error bit in the status register, regardless of the state of the parity error response bit. 7.2.2 ...

Page 85

... The 21154 completes the transaction normally. The 21154 returns to the initiator the data and parity that was received from the target. When the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts PERR# two cycles after the data transfer occurs assumed that the initiator takes responsibility for handling a parity error condition ...

Page 86

... For upstream transactions, in the case where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: • The 21154 asserts s_perr_l two cycles after the data transfer, if both of the following are true: 78 Datasheet ...

Page 87

... The 21154 sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. • The 21154 asserts p_serr_l and sets the signaled system error bit in the status register, if all of the following conditions are met: — The SERR# enable bit is set in the command register. ...

Page 88

... Delayed write 1. x — don’t care. Table 27 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when the 21154 detects a parity error on the secondary interface 80 Bus Where Primary/Secondary Direction Error Was ...

Page 89

... This bit is set under the following conditions: • The 21154 must be a master on the primary bus. • The parity error response bit in the command register, corresponding to the primary interface, must be set. • ...

Page 90

... This bit is set under the following conditions: • The 21154 must be a master on the secondary bus. • The parity error response bit in the bridge control register, corresponding to the secondary interface, must be set. • ...

Page 91

... Table 30 shows assertion of p_perr_l. This signal is set under the following conditions: • The 21154 is either the target of a write transaction or the initiator of a read transaction on the primary bus. • The parity error response bit in the command register, corresponding to the primary interface, must be set. • ...

Page 92

... The 21154 has detected p_perr_l asserted on an upstream posted write transaction or s_perr_l asserted on a downstream posted write transaction. • The 21154 did not detect the parity error as a target of the posted write transaction. • The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. • ...

Page 93

... In compliance with the PCI-to-PCI Bridge Architecture Specification, the 21154 asserts p_serr_l when it detects the secondary SERR# input, s_serr_l, asserted and the SERR# forward enable bit is set in the bridge control register. In addition, the 21154 also sets the received system error bit in the secondary status register. ...

Page 94

... Master timeout on delayed transaction The device-specific p_serr_l status register reports the reason for the 21154’s assertion of p_serr_l. Most of these events have additional device-specific disable bits in the p_serr_l event disable register that make it possible to mask out p_serr_l assertion for specific events. The master timeout condition has a SERR# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit ...

Page 95

... When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the lock on every bus between its bus and the target’s bus. When the 21154 detects, on the primary bus, an initial locked transaction intended for a target on the secondary bus, ...

Page 96

... When the 21154 receives a target abort or a master abort in response to the delayed locked read transaction, a target abort is returned to the initiator, and no locks are established on either the target or the initiator bus. The 21154 resumes forwarding unlocked transactions in both directions. ...

Page 97

... When the 21154 receives a target abort or a master abort in response to a locked posted write transaction, the 21154 cannot pass back that status to the initiator. The 21154 asserts p_serr_l when a target abort or a master abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register ...

Page 98

...

Page 99

... When the primary bus is parked at the 21154 and the 21154 then has a transaction to initiate on the primary bus, the 21154 starts the transaction if p_gnt_l was asserted during the previous cycle ...

Page 100

... Figure 18. Secondary Arbiter Example Each bus master, including the 21154, can be configured either the low priority group or the high priority group by setting the corresponding priority bit in the arbiter control register in device-specific configuration space. Each master has a corresponding bit. If the bit is set to 1, the master is assigned to the high priority group ...

Page 101

... PCI bus is idle. When p_gnt_l is deasserted, the 21154 tristates the p_ad, p_cbe_l, and p_par signals on the next PCI clock cycle. If the 21154 is parking the primary PCI bus and wants to initiate a transaction on that bus, then the 21154 can start the transaction on the next PCI clock cycle by asserting p_frame_l if p_gnt_l is still asserted. ...

Page 102

...

Page 103

... During secondary interface reset, the gpio interface can be used to shift in a 16-bit serial stream that serves as a secondary bus clock disable mask. • A live insertion bit can be used, along with the gpio<3> pin, to bring the 21154 gracefully to a halt through hardware, permitting live insertion of option cards behind the 21154. 10.1 ...

Page 104

... PCI-to-PCI Bridge 10.2 Secondary Clock Control The 21154 uses the gpio pins and the msk_in signal to input a 16-bit serial data stream. This data stream is shifted into the secondary clock control register and is used for selectively disabling secondary clock outputs. The serial data stream is shifted in as soon as p_rst_l is detected deasserted and the secondary reset signal, s_rst_l, is detected asserted ...

Page 105

... These bits control the s_clk_o<8:4> outputs: 0 enables the clock, and 1 disables the clock. Bit 13 is the clock enable bit for s_clk_o<9>, which is connected to the 21154’s s_clk input. If desired, the assignment of s_clk_o clock outputs to slots, devices, and the 21154’s s_clk input can be rearranged from the assignment shown here ...

Page 106

... Figure 20. Clock Mask and Load Shift Timing After the shift operation is complete, the 21154 tristates the gpio signals and can deassert s_rst_l if the secondary reset bit is clear. The 21154 then ignores msk_in. Control of the gpio signal now reverts to the 21154 gpio control registers ...

Page 107

... The 21154 operates at a maximum frequency of 33 MHz MHz if the 21154 is 66 MHz capable. s_clk operates either at the same frequency or at half the frequency as p_clk. ...

Page 108

... After the serial mask has been shifted into the 21154, the value of the mask is readable and modifiable in the secondary clock disable mask register. When the mask is modified by a configuration write operation to this register, the new clock mask disables the appropriate secondary clock outputs within a few cycles ...

Page 109

... The 21154 does not support 33 MHz primary/66 MHz secondary bus operation, where the secondary bus is operating at twice the frequency of the primary bus. If config66 is high and p_m66ena is low (66 MHz capable, primary bus at 33MHz), then the 21154 pulls down s_m66ena to indicate that the secondary bus is operating at 33 MHz. ...

Page 110

...

Page 111

... Support for D0, D1, D2, D3 bridge • Support of the B2 secondary bus power state when in the D3 Table 35 shows the states and related actions that the 21154 performs during power management transitions. (No other transactions are permitted.) Table 35. Power Management Transitions Current State D0 D0 ...

Page 112

...

Page 113

... All posted write and delayed transaction data buffers are reset; therefore, any transactions residing in 21154 buffers at the time of secondary reset are discarded. When s_rst_l is asserted by means of the secondary reset bit, the 21154 remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface ...

Page 114

... PCI-to-PCI Bridge 14.3 Chip Reset The chip reset bit in the diagnostic control register can be used to reset the 21154 and the secondary bus. When the chip reset bit is set, all registers and chip state are reset and all signals are tristated. In addition, s_rst_l is asserted, and the secondary reset bit is automatically set ...

Page 115

... Software changes the configuration register values that affect 21154 behavior only during initialization. Change these values subsequently only when both the primary and secondary PCI buses are idle, and the data buffers are empty; otherwise, the behavior of the 21154 is unpredictable. Datasheet Section 15 ...

Page 116

... Input Data Reserved Power Management Capabilities** Data** * For the 21154-AA, these registers are R/W Subsystem ID and Subsystem Vendor ID. ** These are reserved for the 21154-AA. 15.1 PCI-to-PCI Bridge Standard Configuration Registers This section provides a detailed description of the PCI-to-PCI bridge standard configuration registers ...

Page 117

... Primary Command Register—Offset 04h This section describes the primary command register. These bits affect the behavior of the 21154 primary interface, except where noted. Some of the bits are repeated in the bridge control register, to act on the secondary interface. This register must be initialized by configuration software. ...

Page 118

... R/W initiate I/O or memory transactions on the primary interface. When 1: The 21154 is enabled to operate as an initiator on the primary bus and responds to I/O and memory transactions initiated on the secondary bus. Reset value: 0. The 21154 ignores special cycle transactions, so this bit is R read only and returns 0 ...

Page 119

... Primary Status Register—Offset 06h This section describes the primary status register. These bits affect the status of the 21154 primary interface. Bits reflecting the status of the secondary interface are found in the secondary status register. W1TC indicates that writing bit sets that bit to 0. Writing 0 has no effect. ...

Page 120

... This bit is set to 1 when the 21154 is acting as a target on the primary bus and returns a target abort to the R/W1TC primary master. Reset value: 0. This bit is set to 1 when the 21154 is acting as a master on the primary bus and receives a target abort from the R/W1TC primary target. Reset value: 0. ...

Page 121

... Dwords. Used for prefetching memory read transactions and for terminating memory write and invalidate transactions. R/W The cache line size should be written as a power the value is not a power greater than 16, the 21154 behaves as if the cache line size were 0. Reset value: 0. 21154 PCI-to-PCI Bridge ...

Page 122

... Master latency timer for the primary interface. Indicates the number of PCI clock cycles from the assertion of p_frame_l to the expiration of the timer when the 21154 is acting as a master on the primary interface. All bits are writable, resulting in a granularity of one PCI clock cycle. ...

Page 123

... Reset value: 0. R/W Description Indicates the number of the highest numbered PCI bus that is behind (or subordinate to) the 21154. Used in conjunction with the secondary bus number to determine when to respond to Type 1 configuration R/W transactions on the primary interface and pass them to the secondary interface as a Type 1 configuration transaction ...

Page 124

... Master latency timer for the secondary interface. Indicates the number of PCI clock cycles from the assertion of s_frame_l to the expiration of the timer when the 21154 is acting as a master on the secondary interface. All bits are writable, resulting in a granularity of one PCI clock cycle. ...

Page 125

... Secondary Status Register—Offset 1Eh This section describes the secondary status register. These bits reflect the status of the the 21154 secondary interface. W1TC indicates that writing 1 to that bit sets the bit to 0. Writing 0 has no effect. Dword address = 1Ch Byte enable p_cbe_l<3:0> = 00xxb ...

Page 126

... Byte enable p_cbe_l<3:0> = 00xxb 118 R/W Description (Sheet This bit is set to 1 when the 21154 is acting as a master on the secondary bus and receives a target R/W1TC abort from the secondary bus target. Reset value: 0. This bit is set to 1 when the 21154 is acting as an ...

Page 127

... Defines the bottom address of an address range used by the 21154 to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits are writable and correspond to address bits <31:20>. ...

Page 128

... Reset value: 0. R/W Description Defines the upper 32 bits of a 64-bit bottom address of an address range used by the 21154 to determine when to forward memory read and write transactions from one interface to the other. R/W The memory address range adheres to 1MB alignment and granularity. ...

Page 129

... Reset value: 0. R/W Description Defines the upper 16 bits of a 32-bit bottom address of an address range used by the 21154 to determine when to forward I/O transactions from one interface R/W to the other. The I/O address range adheres to 4KB alignment and granularity. Reset value: 0. ...

Page 130

... Reset to 0. R/W Description Enhanced capabilities port (ECP) offset pointer. Reads as DCh in the 21154–AB and later revisions to indicate that the first item, which corresponds to R the power management registers, resides at that configuration offset. This is a R/W register with no side effects in the 21154– ...

Page 131

... Description Controls the 21154’s response when a parity error is detected on the secondary interface. When 0: The 21154 does not assert s_perr_l, nor does it set the data parity reported bit in the secondary status register. The 21154 does not report address parity errors by asserting p_serr_l ...

Page 132

... FFFF FFFFh for read transactions. For posted write R/W transactions, p_serr_l is not asserted. When 1: The 21154 returns a target abort on the initiator bus for delayed transactions. For posted write transactions, the 21154 asserts p_serr_l if the SERR# enable bit is set in the command register. ...

Page 133

... Master timeout 27 SERR# enable 31:28 Reserved 15.1.32 Capability ID Register—Offset DCh This section describes the capability ID register. (Implemented in the 21154–AB and later revisions only. In the 21154–AA, this register is reserved.) Dword address = DCh Byte enable p_cbe_l<3:0> = xxx0b Dword Bits Name 7:0 CAP_ID Datasheet ...

Page 134

... PCI-to-PCI Bridge 15.1.33 Next Item Ptr Register—Offset DDh This section describes the next item ptr register. (Implemented in the 21154–AB and later revisions only. In the 21154–AA, this register is reserved.) Dword address = DCh Byte enable p_cbe_l<3:0> = xx0xb Dword Bit ...

Page 135

... DATA_ 14:13 SCALE 15 PME_STAT 15.1.36 PPB Support Extensions Registers—Offset E2h This section describes the PPB support extensions registers. (Implemented in the 21154–AB and later revisions only. In the 21154–AA, these registers are reserved.) Dword address = E0h Byte enable p_cbe_l<3:0> = x0xxb Datasheet R/W Description Power State ...

Page 136

... Data 15.2 Device-Specific Configuration Registers This section provides a detailed description of the 21154 device-specific configuration registers. Each field has a separate description. Fields that have the same configuration address are selectable by turning on (driving low) the appropriate byte enable bits on p_cbe_l during the data phase. To select all fields of a configuration address, drive all byte enable bits low ...

Page 137

... R/W Description R Reserved. Returns 0 when read. Controls when the 21154 target, disconnects memory write transactions. When 0: The 21154 disconnects on queue full 4KB boundary. R/W When 1: The 21154 disconnects on a cache line boundary, as well as when the queue fills 4KB boundary. Reset value: 0. ...

Page 138

... When 1: Causes the 21154 to perform a chip reset. Data buffers, configuration registers, and both the primary and secondary interfaces are reset to their initial state. The 21154 clears this bit once chip reset is R/W1TR complete. The 21154 can them be reconfigured. Secondary bus reset s_rst_l is asserted and the secondary reset bit in the bridge control register is set when this bit is set ...

Page 139

... When 1: Signal p_serr_l is not asserted if this event occurs. Reset value: 0. Controls the 21154’s ability to assert p_serr_l when it receives a master abort when attempting to deliver posted write data. When 0: Signal p_serr_l is asserted if this event occurs and the SERR# enable bit in the command R/W register is set ...

Page 140

... SERR# enable bit in the command R/W register is set. When 1: Signal p_serr_l is not asserted if this event occurs. Reset value: 0. Controls the 21154’s ability to assert p_serr_l when it is unable to transfer any read data from 24 the target after 2 attempts. When 0: Signal p_serr_l is asserted if this event ...

Page 141

... When read, reflects the last value written. Reset value: 0 (all pins are input only). R/W Description R Reserved. Returns 0 when read. This read-only register reads the state of the gpio<3:0> R pins. This state is updated on the PCI clock cycle following a change in the gpio pins. 21154 PCI-to-PCI Bridge 133 ...

Page 142

... PCI-to-PCI Bridge Dword Bit Name Slot 0 clock 1:0 disable Slot 1 clock 3:2 disable Slot 2 clock 5:4 disable Slot 3 clock 7:6 disable Device 1 8 clock disable Device 2 9 clock disable Device 3 10 clock disable Device 4 11 clock disable 134 R/W Description If either bit is 0: Signal s_clk_o<0> is enabled. ...

Page 143

... Reserved 15.2.9 p_serr_l Status Register—Offset 6Ah This section describes the p_serr_l status register. This status register indicates the reason for the 21154’s assertion of p_serr_l. Dword address = 68h Byte enable p_cbe_l<3:0> = x0xxb Dword Bit Name Address parity 0 error Posted write ...

Page 144

... Configuration Register Values After Reset Table 36 lists the value of the 21154 configuration registers after reset. Reserved registers are not listed and are always read only as 0. Table 36. Configuration Register Values After Reset (Sheet Byte Address Register Name 00— ...

Page 145

... Power management data register 1. Dependent on revision of device. 2. The value of this register is dependent upon the serial clock disable shift function that occurs during secondary bus reset the 21154–AA, these registers are reserved. Datasheet Reset Value 0001h 00000000h 00000000h 0000h 0000h ...

Page 146

...

Page 147

... A test access port controller • An instruction register • A bypass register • A boundary-scan register Note: The JTAG test access port used only while the 21154 is not operating. 16.2 JTAG Signal Pins This chapter describes the JTAG pins listed in Table 37. JTAG Pins Signal Name ...

Page 148

... Instruction Register The 5-bit instruction register selects the test modes and features. The instruction register bits are interpreted as instructions, as shown in of the boundary-scan and bypass registers. Table 38 describes the 21154’s instructions. Table 38. JTAG Instruction Register Instruction Instruction Name Register (Test Mode or ...

Page 149

... D1 s_req_l<5> D2 s_req_l<6> E3 s_req_l<7> E1 s_req_l<8> E2 s_gnt_l<0> F3 s_gnt_l<1> F1 s_gnt_l<2> Datasheet Table 39 shows which group disable bit controls the Boundary-Scan By Group Group Disable Cell Order Disable 88 — 89 — 90 — 91 — 92 — 93 — 94 — 95 — 96 — 21154 PCI-to-PCI Bridge 141 ...

Page 150

... PCI-to-PCI Bridge Table 39. Boundary Scan Order (Sheet Pin Signal Name Number F2 s_gnt_l<3> — Vss G1 s_gnt_l<4> G4 s_gnt_l<5> G2 s_gnt_l<6> G3 s_gnt_l<7> H1 s_gnt_l<8> H2 s_rst_l J4 s_clk K1 s_cfn_l K2 gpio<3> K3 gpio<2> L4 gpio<1> L1 gpio<0> L2 s_clk_o<0> — Vss L3 s_clk_o<1> M3 s_clk_o<2> M1 s_clk_o<3> M2 s_clk_o<4> N3 s_clk_o<5> N1 s_clk_o<6> P3 s_clk_o<7> P2 s_clk_o<8> P1 s_clk_o<9> ...

Page 151

... Group Disable 2 149 2 150 1 151 1 152 1 153 1 154 1 155 1 156 — Group Disable 1 157 1 158 1 159 0 160 0 161 0 162 0 163 0 164 0 165 0 166 0 167 0 168 0 169 0 170 0 171 0 172 0 173 0 21154 PCI-to-PCI Bridge 143 ...

Page 152

... PCI-to-PCI Bridge Table 39. Boundary Scan Order (Sheet Pin Signal Name Number AB12 p_ad<4> AB13 p_ad<3> AA13 p_ad<2> Y13 p_ad<1> AA14 p_ad<0> AB14 p_ack64_l AC14 p_req64_l AA15 p_cbe_l<7> AB15 p_cbe_l<6> Y15 p_cbe_l<5> AC15 p_cbe_l<4> AA16 p_ad<63> AB16 p_ad<62> AA17 p_ad< ...

Page 153

... PCI-to-PCI Bridge 145 ...

Page 154

... PCI-to-PCI Bridge Table 39. Boundary Scan Order (Sheet Pin Signal Name Number E20 s_ad<56> D21 s_ad<57> C22 s_ad<58> C23 s_ad<59> C21 s_ad<60> D20 s_ad<61> A21 s_ad<62> C20 s_ad<63> D19 s_cbe_l<4> A20 s_cbe_l<5> C19 s_cbe_l<6> A19 s_cbe_l<7> B19 s_req64_l C18 ...

Page 155

... Group Disable Cell Order Disable — Group Disable — Group Disable 21154 PCI-to-PCI Bridge 147 ...

Page 156

...

Page 157

... Absolute Maximum Ratings The 21154 is specified to operate at a maximum frequency of 33 MHz MHz if 66 MHz capable junction temperature (T ratings for the 21154. These are stress ratings only; stressing the device beyond the absolute maximum ratings may cause permanent damage. Operating beyond the functional operating range ...

Page 158

... PCI-to-PCI Bridge 17.3 DC Specifications Table 42 defines the dc parameters met by all 21154 signals under normal operating conditions. Table 42. DC Parameters Symbol Parameter V Supply voltage cc V Low-level input voltage il V High-level input voltage ih V Low-level output voltage ol V Low-level output voltage ol5V ...

Page 159

... V high skew skew T cyc for 3.3-V clocks cc for 3.3-V clocks cc for 3.3-V clocks cc Minimum — 2 — 21154 PCI-to-PCI Bridge Table 43 Figure 24 41. low low LJ-04738.AI4 Maximum Unit ns — ns — V/ 0.750 ns 0.500 ns and ...

Page 160

... PCI-to-PCI Bridge Table 44. 66 MHz PCI Clock Signal AC Parameters Symbol Parameter T p_clk,s_clk cycle time cyc T p_clk, s_clk high time high T p_clk, s_clk low time low p_clk, s_clk slew rate T Delay from p_clk to s_clk sclk T p_clk rising to s_clk_o rising sclkr ...

Page 161

... Datasheet Minimum Maximum 7 — 10, 12 — 1,2 0 — Minimum Maximum 1,2 2 — 1,2 — — 5 — 1,2 0 — 21154 PCI-to-PCI Bridge Unit Unit 153 ...

Page 162

... PCI-to-PCI Bridge 17.4.3 Reset Timing Specifications Table 47 shows the reset timing specifications for p_rst_l and s_rst_l. Table 47. Reset Timing Specifications Symbol Parameter T p_rst_l active time after power stable rst T p_rst_l active time after p_clk stable rst—clk T p_rst_l active-to-output float delay rst— ...

Page 163

... PCI-to-PCI Bridge Minimum Unit 12 ns — — ...

Page 164

...

Page 165

... Mechanical Specifications The 21154 is contained in an industry-standard 304-point 2-layer plastic ball grid array (PBGA) package, shown in Figure Figure 25. 304-Point 2-Layer PBGA Package Pin 1 Corner Pin 1 I. Chamfer 4 Places Datasheet 25 ...

Page 166

... PCI-to-PCI Bridge Table 51 lists the package dimensions in millimeters. Table 51. 304-Point 2-Layer PBGA Package Dimensions Symbol Dimension e Ball Pitch A Overall package height A Package standoff height 1 A Encapsulation thickness 2 b Ball diameter c Substrate thickness aaa Coplanarity bbb Overall package planarity D Overall package width ...

Page 167

...

Page 168

Support, Products, and Documentation If you need technical support, a Product Catalog, or help deciding which documentation best meets your needs, visit the Intel World Wide Web Internet site: http://www.intel.com Copies of documents that have an ordering number and are ...

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