21154-AB

Manufacturer Part Number21154-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21154-AB datasheet
 


Specifications of 21154-AB

CaseBGADc99+
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Page 1/168

Download datasheet (728Kb)Embed
Next
21154 PCI-to-PCI Bridge
Product Features
Complies fully with the PCI Local Bus
Specification, Revision 2.1
Complies fully with the PCI Power
Management Specification, Revision 1.0
Supports 64-bit extension signals on the
primary and secondary interfaces
Implements delayed transactions for all PCI
configuration, I/O, and memory read
commands–up to three transactions
simultaneously in each direction
Allows 152 bytes of buffering (data and
address) for upstream posted memory write
commands and 88 bytes of buffering for
downstream posted memory write
commands—up to nine upstream and five
downstream posted write transactions
simultaneously
Allows 152 bytes of read data buffering
upstream and 152 bytes of read data
buffering downstream
Provides concurrent primary and secondary
bus operation to isolate traffic
Provides ten secondary clock outputs:
— Low skew, permitting direct drive of
option slots
— Individual clock disables, capable of
automatic configuration during reset
Provides arbitration support for nine
secondary bus devices:
— A programmable 2-level arbiter
— Hardware disable control, permitting use
of an external arbiter
1.
For the 21154–AB and later revisions only. The 21154–AA does not implement this feature.
Datasheet
Provides a 4-pin general-purpose I/O
interface, accessible through device-
specific configuration space
1
Provides enhanced address decoding:
— A 32-bit I/O address range
— A 32-bit memory-mapped I/O address
range
— A 64-bit prefetchable memory address
range
— ISA-aware mode for legacy support in
the first 64KB of I/O address range
— VGA addressing and VGA palette
snooping support
Includes live insertion support
Supports PCI transaction forwarding for the
following commands:
— All I/O and memory commands
— Type 1 to Type 1 configuration
commands
— Type 1 to Type 0 configuration
commands (downstream only)
— All Type 1 to special cycle configuration
commands
Includes downstream lock support
Supports both 5-V and 3.3-V signaling
environments
Available in both 33 MHz and 66 Mhz
versions
Provides an IEEE standard 1149.1 JTAG
interface
Order Number: 278108-002
July 1999

21154-AB Summary of contents