SK70721PE Intel Corporation, SK70721PE Datasheet
SK70721PE
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SK70721PE Summary of contents
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SK70720 and SK70721 Multi-Rate DSL Data Pump Chip Set The Multi-Rate DSL Data Pump is a complete, variable-rate transceiver that provides full duplex communication on two wires using echo-canceller-with-hybrid and 2B1Q line coding technology. It provides symmetrical line rates from ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ...
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Contents 1.0 Features ......................................................................................................................... 7 2.0 Pin Assignment and Signal Descriptions 3.0 Functional Description 3.1 Framing ...............................................................................................................16 3.1.1 Fixed Data Rate Mode ...........................................................................17 3.1.2 Variable Data Rate Mode .......................................................................18 3.2 Component Description.......................................................................................19 3.2.1 Integrated Analog Front End (IAFE).......................................................19 3.2.2 MDSL ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set 7.0 Mechanical Specifications Figures 1 SK70720 and SK70721 Block Diagram ................................................................ 8 2 SK70721 IAFE Pin Locations................................................................................ 9 3 SK70720 MDSP Pin Assignments ...................................................................... 11 4 MDSL System Data Transport ...
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IAFE DC Electrical Characteristics (Over Recommended Range)......................40 16 IAFE Transmitter Electrical Parameters (Over Recommended Range)..............41 17 IAFE Receiver Electrical Parameters (Over Recommended Range) ..................42 18 MDSP Absolute Maximum Ratings .....................................................................45 19 MDSP Recommended Operating Conditions......................................................45 20 MDSP DC Electrical ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Revision History Revision Date 6 Description Datasheet ...
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Features • Fully integrated, 2-chip transceiver • Compliant with the following standards: — ITU G.991.1 — ANSI Committee T1E1 .4-TR28 (T1E1.4/96-006) — ETSI ETR -152 • Integrated line drivers, filters and hybrid circuits reduce the number of external components ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Figure 1. SK70720 and SK70721 Block Diagram SLAVE_CK TDATA TFP RDATA RFP BIT_CK MODE ACTIVE MSTR_CK DATA ADDR CTRL 8 MDSP Back End Scrambler Control Activation Logic Control Echo Canceller ...
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... Multi-Rate DSL Data Pump Chip Set — SK70720 and SK70721 Figure 2 shows the IAFE pin locations and Figure Rev # Part # SK70721PE XX LOT # XXXXXX XXXXXXXX FPO # Definition Table 1 lists shows MDSP pin designations and TSGN 25 24 ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set FPO # Identifies the Finish Process Order. Table 1. SK70721 IAFE Pin Assignments/Signal Descriptions Group Pin # Symbol 13 RTIP 14 RRING 16 BTIP Line 17 BRING 21 TTIP 22 ...
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Figure 3. SK70720 MDSP Pin Assignments 6 RFP 7 RDATA 8 ADDR3(ACTVNG) 9 RDATA_ST 10 TDATA 11 TFP 12 MSTR_CK 13 SLAVE_CK 14 CK_EN 15 MODE 16 BIT_CK ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Table 2. SK70720 MDSP Pin Assignments/Signal Descriptions Group Pin # Symbol 1 VCC1 44 VCC2 Power 2 GND1 3 GND2 28 GND3 29 n/c Misc 31 TEST 18 RESET 10 ...
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Table 2. SK70720 MDSP Pin Assignments/Signal Descriptions (Continued) Group Pin # Symbol 4 QUIET 5 ACTREQ 6 LOOPID 9 ACTVNG 32 TMR_EXP 33 CHIPSEL 34 WRITE Hardware 35 READ Interface (Hardware Control LOS Mode) (Master) 36 LOS (Slave) 37 DEACTVTD ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Table 2. SK70720 MDSP Pin Assignments/Signal Descriptions (Continued) Group Pin # Symbol 40 FELB Hardware 41 BELB Interface (Hardware Control 42 RCLKU Mode) -cont’d 43 TXTST ...
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Table 2. SK70720 MDSP Pin Assignments/Signal Descriptions (Continued) Group Pin # Symbol 14 SLAVE_CK 15 CK_EN 13 MSTR_CK 19 VCO_CK Clock and Control 20 SER_CTL 21 RX_CK 22 AD0 23 AD1 24 AGC_SET 25 TX_CK 26 TMAG 27 TSGN 1. ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set 3.0 Functional Description The MDSL Data Pump (MDP) provides synchronous, full duplex transmission on a single pair of wires using 2B1Q line coding and echo cancellation. The Data Pump supports ...
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Figure 4. MDSL System Data Transport BIT_CK b4701 b4702 XXX TDATA TFP TDATA TFP BIT_CK RFP RDATA RDATA_ST Master Data Pump Figure 5. MDSL Frame MDSL Frame The MDP receiver detects the incoming FSW and ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set than to create a fixed mapping between specific time slots in the MDSL and application frames. With unframed, time-division multiplexed data defined relative to an application frame pulse it is ...
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Component Description The following paragraphs describe the chip set components individually with reference to internal functions and the interfaces between Data Pump components. 3.2.1 Integrated Analog Front End (IAFE) The IAFE incorporates the following analog functions: • the transmit ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set • fixed and adaptive digital-filtering functions • activation/start-up control and the microprocessor interface The MDSP also provides the digital data interface. A simple, parallel 8-bit microprocessor interface on the MDSP ...
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MDSP/IAFE Serial Port The MDSP continually writes to the IAFE serial port. This serial stream consists of two 16-bit words as shown in Table Refer to the Test Specifications section for serial port timing relationships and electrical parameters. 3.3 ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Figure 7. MDSP/IAFE Interface – Relative Timing VCO_CK TX_CK VCO_CK/2 RX_CK AD0 AD1 SER_CTL 3.4 MDSL Data Interface This section provides detailed information on the operation of the data interface ...
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The Master transceiver requires a clock frequency of: MSTR_CK = 16 (line_rate). The slave transceiver requires a clock frequency of: SLAVE_CK = 16 (line_rate). Both transceivers require a VCXO crystal frequency of: fxtal = 32 (line_rate). Figure 8. MDSL Clock ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Both transceivers require a VCXO crystal frequency of: fxtal = 32 (line_rate). 3.4.4 Data Interface Timing The MDSL data interface provides for the transfer of binary data to and from ...
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Figure 9. MDSP Digital Data Interface Timing A) Transmit Timing–Without Stuff Bits BIT_CK TFP b4699 b4701 TDATA b4700 b4702 b1-b14 are the frame sync word generated by the MDSP (not sampled from TDATA) B) Transmit Timing–With Stuff Bits BIT_CK TFP ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set 3.5.1 Control Pins Chip Select: The Chip Select (CHIPSEL) pin requires an active Low signal to enable Data Pump read or write transfers over the data bus. To enable Hardware ...
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Drive CHIPSEL Low. 2. Drive the desired address onto ADDR0-ADDR3. 3. Pull READ Low, observing minimum pulse width. 4. Pull READ High to complete the read cycle. Registers RD3 and RD4 hold the coefficient values from the DFE, EC, ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Successful detection of the sync word drives the State machine to the Active-1 State. This is indicated by a 0-to-1 transition of the ACTIVE bit or High to Low transition ...
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Figure 10. Master Mode Activation State Machine DEACTVTD 0 1 Pending Deactivation ACTIVE 1 0 Active ( NOTE: ( indicates the status of bits ST2, ST1 and ST0 respectively. ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Table 8. Data Pump Activation States ST2 ST1 The data pump samples the ...
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Synchronization State Machine Figure 12 shows the MDSL Synchronization State Machine incorporated in the MDSP. It applies to both Master and Slave devices. states and Activation states. The Sync state machine is clocked by the receive signal framing. Starting ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Figure 12. MDSL Synchronization State Machine No Sync Initial "Out-of-Sync" State 0 ACTIVE = 0 LOS = 1 LOS = 1 or DEACTVTD = 1 Out of Sync State 8 ...
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Application Information 4.1 PCB Layout Refer to Figure 13, considerations for PCB layout using the MDSL Data Pump chip set: 1. Use a four-layer or more PCB layout, with embedded power and ground planes 2. Bring the digital power ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set The following are considerations for PCB layout of analog signals: 1. Route digital signals AD0, AD1, RX_CK, SER_CTL, TSGN, TMAG, TX_CK, and AGC_SET on the solder side of the PCB ...
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Figure 13. PCB Layout Guidelines VCC GND NOTE: The VCC and GND planes for Digital and Analog sides should be connected at a single point. Datasheet Multi-Rate DSL Data Pump Chip Set — SK70720 ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Figure 14. Typical Application for Master Mode Operation (Microprocessor Interface Mode) + C10 RFP TSGN 10 RDATA_ST TMAG 8 RDATA ...
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Table 10. Components for Suggested Circuitry (Figure 14 and Figure 15) (Continued) Ref Description C5, 6 470 pF, COG or mica, 10% C7, 11-13 0.1 F, ceramic, 10% C8 100 F, electrolytic, 20% 1. R7, R8 should ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Table 11. Transformer Specifications (Figure 14 and Figure 15, Reference T1) Measure Turns Ratio (IC:Line) Line Side Inductance 400 kbps < 400 kbps Leakage Inductance Interwinding Capacitance THD Longitudinal Balance ...
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Figure 16. MDSP Control and Status Signals (Stand-alone Mode) NOTE: This figure illustrates the MDSP control and status signals in stand-alone mode. All other MDSP and IAFE signals are connected as shown in Figure 14 Datasheet Multi-Rate DSL Data Pump ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set 5.0 Test Specifications Note: The minimum and maximum values in represent the performance specifications of the Data Pump and are guaranteed by test, except where noted by design. Table 13. ...
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Table 16. IAFE Transmitter Electrical Parameters (Over Recommended Range) Parameters Sym – – Isolated pulse height at TTIP, TRING – – Setup time (TSGN, TMAG) t TSMSU Hold time (TSGN, TMAG) t TSMH 1. Pulse amplitude measured across a 135 ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Figure 18. Transmit Power Spectral Density—Upper Bound -20 -40 -60 -80 -100 -120 -140 1 kHz IAFE Receiver Electrical Parameters Table 17. Parameter Propagation delay (AD0, AD1) Total harmonic distortion ...
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Figure 19. IAFE Receiver Syntax and Timing A) Receiver Syntax VCO_CK VCO_CK/2 (INTERNAL) RX_CK AD0 AD1 AGC_SET Datasheet Multi-Rate DSL Data Pump Chip Set — SK70720 and SK70721 VCO_CK AD0, AD1 AGC_SET B) Receiver Timing PROP DELAY 43 ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Figure 20. Typical Performance vs. Line Rate and Cable Gauge (Metric) 8,000 7,500 7,000 6,500 6,000 5,500 5,000 4,500 4,000 3,500 3,000 2,500 2,000 272 336 NOTES: 1. Noise-free range ...
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Figure 21. Typical Performance vs. Line Rate and Cable Gauge (English) 30,000 25,000 20,000 15,000 10,000 5,000 0 272 336 NOTES: 1. Noise-free range is specified with a Bit Error Rate (BER) less than or equal to 1 ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Table 20. MDSP DC Electrical Characteristics (Over Recommended Range) Parameter 272 kbps 400 kbps Supply current 528 kbps 784 kbps Input low voltage Input high voltage 2 Output low voltage ...
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Table 21. MDSL Data Interface Timing Specifications (Figure 22) (Continued) Parameter 4 TFP pulse width 4 TFP falling edge to BIT_CK rising edge TFP set-up time to MSTR_CK rising edge 1. Typical values are at 25° C and are for ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Figure 22. MDSL Data Interface Timing A) Non-Repeater Mode BIT_CK TDATA, TFP RATA, RFP, RDATA_ST B) Repeater Mode TFP BIT_CK TDATA RATA, RFP, RDATA_ST C) Repeater Mode MSTR_CK TFP 48 ...
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Table 22. MDSP/Microprocessor Interface Timing Specifications (Figure 19 & Figure 20) Parameter RESET pulse width Low RESET to INT clear (10 k resistor from INT to VCC2) RESET to data tristate on D0-7 CHIPSEL pulse width Low CHIPSEL Low to ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Figure 23. RESET and INTERRUPT Timing ( P Control Mode) A) Reset Timing RESET INT D<0:7> (Output) B) Interrupt Timing READ CHIPSEL ADDR<0:3> INT 50 t RPWL t INTH t ...
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Figure 24. Parallel Data Channel Timing A) Chip Select Timing CHIPSEL (READ = 0) D<0:7> (Output) B) Data Read Timing CHIPSEL ADDR<0:3> READ (WRITE = 1) D<0:7> (Output) C) Data Write Timing CHIPSEL ADDR<0:3> WRITE (READ = 1) D<0:7> (Input) ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set 6.0 Register Definitions Three write registers and seven read registers are available to the user. and the following paragraphs describe them in greater detail. Some of the registers contain reserved ...
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Table 25. Main Control Register WR0 (Continued) Bit Loop Number (LOOPID). In two loop MDSL applications, LOOPID is set at the Master end of the loop to select the 3 frame sync word format to encode the loop number. Insertion ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Table 27. Read Coefficient Select Register WR3 Hex Value 00-07 08-0F 10-15 16-19 1A 1B-FF 6.0.4 RD0—Main Status Register Address: A<3:0> = 0000 Default: xxh (x = undefined) Attributes: Read ...
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RD1—Receiver Gain Word Register Address: A<3:0> = 0001 Default: xxh (x = undefined) Attributes: Read Only The 8-bit word in this register is the eight most significant bits of the main FFE AGC tap, which, along with the AGC ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Table 30. Noise Margin Register RD2 (Continued) (Noise Margin Coding) MSB ...
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Table 31. Coefficient Read Register Bit 7:0 Coefficient Word Value. RD3 contains the lower byte; RD4 the upper byte. 6.0.8 RD5—Activation Status Register Address: A<3:0> = 0101 Default: xxh (x = undefined) Attributes: Read Only The ACT bits indicate the ...
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SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set Table 33. Receiver AGC and FFE Step Gain Register RD6 Bit 7 ST2. Data Pump Activation State–bit 2. 6 ST1. Data Pump Activation State–bit 1. GFFE1, GFFE0. Digital Gain Word–bit ...
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... Mechanical Specifications Figure 25. Data Pump Package Specifications Integrated Analog Front End (IAFE) • 28-pin PLCC • P/N SK70721PE • Extended Temperature Range (-40° 85° Inches Dim Min Max A 0.165 0.180 A1 0.090 0.120 A2 0.062 0.083 1 B .050 ...
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