LXT9785BC Intel Corporation, LXT9785BC Datasheet
LXT9785BC
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LXT9785BC Summary of contents
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LXT9785 Advanced 10/100 8-Port PHY The LXT9785 is an 8-port Fast Ethernet PHY Transceiver that supports IEEE 802.3 physical layer applications at both 10Mbps and 100Mbps. This device provides both Serial/Source Synchronous (SMII/SS-SMII) and Reduced Media Independent (RMII) Interfaces for ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ® ...
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Contents 1.0 Pin Assignments and Signal Descriptions 1.1 Signal Name Conventions...................................................................................39 2.0 Functional Description 2.1 Introduction..........................................................................................................51 2.1.1 OSP™ Architecture ................................................................................51 2.1.2 Comprehensive Functionality .................................................................51 2.1.2.1 Sectionalization .........................................................................52 2.2 Interface Descriptions..........................................................................................52 2.2.1 10/100 Network Interface .......................................................................52 2.2.1.1 Twisted-Pair Interface ...............................................................53 2.2.1.2 ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.6.1.3 Controlling Auto-Negotiation ..................................................... 63 2.6.1.4 Link Criteria ............................................................................... 63 2.6.1.5 Parallel Detection ...................................................................... 63 2.7 Serial MII Operation ............................................................................................ 64 2.7.1 SMII Reference Clock ............................................................................ 67 2.7.2 TxSYNC Pulse (SMII/SS-SMII) .............................................................. 67 2.7.3 ...
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MII Terminations.....................................................................................89 3.2.4 Twisted-Pair Interface ............................................................................90 3.2.4.1 Magnetics Information ...............................................................90 3.2.5 The Fiber Interface .................................................................................90 3.2.6 LED Circuit .............................................................................................90 3.3 Typical Application Circuits .................................................................................92 4.0 Test Specifications 5.0 Register Definitions 6.0 Package Specifications Datasheet Advanced 10/100 8-Port PHY — ...
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LXT9785 — Advanced 10/100 8-Port PHY Figures 1 LXT9785 Block Diagram ..................................................................................... 11 2 LXT9785 RMII 208-Pin PQFP Assignments ....................................................... 12 3 LXT9785 SMII 208-Pin PQFP Assignments ....................................................... 13 4 LXT9785 SS-SMII 208-Pin PQFP Assignments ................................................. 14 5 LXT9785 RMII ...
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... Power-Up Timing...............................................................................................118 59 Reset Recovery Timing .....................................................................................118 60 PHY Identifier Bit Mapping ................................................................................122 61 LXT9785 208-Pin PQFP Plastic Package Specification....................................136 62 LXT9785 241-Ball PBGA Package Specification (LXT9785BC) .......................137 Tables 1 RMII PQFP Pin List .............................................................................................18 2 SMII PQFP Pin List .............................................................................................25 3 SS-SMII PQFP Pin List .......................................................................................32 4 LXT9785 RMII Signal Descriptions ...
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LXT9785 — Advanced 10/100 8-Port PHY 35 SMII - 100BASE-TX Transmit Timing Parameters .............................................. 99 36 SMII - 100BASE-FX Receive Timing Parameters ............................................. 100 37 SMII - 100BASE-FX Transmit Timing Parameters ............................................ 101 38 SMII - 10BASE-T Receive Timing Parameters ...
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Revision History Date Revision January 2001 002 Global: Add bar to all LEDm_n for active low status. Tables 1, 2 and 3: Add RMII, SMII, and SS-SMII numeric pin lists. Introduction: Deleted “(up to 100 meters)” and “(up to 185 ...
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Figure 1. LXT9785 Block Diagram RMII/SMII Contr ADD_<4:0> Management / Mode Select MDIO 2 Logic & LED MDC 2 MDINT 2 Register Set TXDn Parallel/Serial Mgmt Counters Register Set Port LED Drivers 3 LEDn_<2:0> RXDn Carrier Sense Data Valid Error ...
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LXT9785 — Advanced 10/100 8-Port PHY 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT9785 RMII 208-Pin PQFP Assignments CRS_DV6 ..... 1 RXER6 ..... 2 TXEN6 ..... 3 TXD6_0 ..... 4 TXD6_1 ..... 5 REFCLK1 ..... 6 RXD5_1 ..... 7 ...
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Figure 3. LXT9785 SMII 208-Pin PQFP Assignments N/C ..... 1 N/C ..... 2 N/C ..... 3 TXD6 ..... 4 N/C ..... 5 REFCLK1 ..... 6 N/C ..... 7 RXD5 ..... 8 GNDIO ..... 9 N/C ..... 10 N/C ..... 11 ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 4. LXT9785 SS-SMII 208-Pin PQFP Assignments N/C ..... 1 N/C ..... 2 N/C ..... 3 TXD6 ..... 4 N/C ..... 5 REFCLK1 ..... 6 RXD5 ..... 7 N/C ..... 8 GNDIO ..... 9 ...
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Figure 5. LXT9785 RMII 241-Ball PBGA Assignments RMI CRS_D A GNDD VCCIO RXD1_0 TXD2_1 V2 B RXD0_1 TXEN1 GNDD RXD1_1 TXD2_0 CRS_D C VCCIO RXD0_0 TXD1_0 GNDD V1 RXER0/ RXER1/ D GNDD GNDD TXD1_1 ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 6. LXT9785 SMII 241-Ball PBGA Assignments SMI GNDD VCCIO RXD1 N/C N/C B N/C N/C GNDD N/C TXD2 C VCCIO RXD0 TXD1 N/C GNDD D GNDD ...
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Figure 7. LXT9785 SS-SMII 241-Ball PBGA Assignments SS- SMI GNDD VCCIO N/C N/C N/C B RXD0 N/C GNDD RXD1 TXD2 C VCCIO RXD0 TXD1 N/C GNDD D GNDD MDIX GNDD N/C PAUSE RX_ ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 1. RMII PQFP Pin List Pin Symbol 1 CRS_DV6 2 RXER6 3 TXEN6 4 TXD6_0 5 TXD6_1 6 REFCLK1 7 RXD5_1 8 RXD5_0 9 GNDIO 10 CRS_DV5 11 RXER5 12 TXEN5 13 TXD5_0 ...
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Table 1. RMII PQFP Pin List (Continued) Pin Symbol 34 TXD3_0 35 TXD3_1 36 RXD2_1 37 RXD2_0 38 GNDIO 39 CRS_DV2 40 RXER2 41 TXEN2 42 TXD2_0 43 TXD2_1 44 REFCLK0 45 RXD1_1 46 RXD1_0 47 VCCIO 48 GNDIO 49 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 1. RMII PQFP Pin List (Continued) Pin Symbol 68 LED3_3 69 LED3_2 70 LED3_1 71 LED2_3 72 LED2_2 73 LED2_1 74 GNDIO 75 LED1_3 76 LED1_2 77 LED1_1 78 VCCD 79 GNDD 80 ...
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Table 1. RMII PQFP Pin List (Continued) Pin Symbol 102 N/C 103 VCCR0 104 TPFIP0 105 TPFIN0 106 GNDR0 107 TPFOP0 108 TPFON0 109 VCCT0/1 110 TPFON1 111 TPFOP1 112 GNDR1 113 GNDT0/1 114 TPFIN1 115 TPFIP1 116 VCCR1 117 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 1. RMII PQFP Pin List (Continued) Pin Symbol 136 TPFOP4 137 TPFON4 138 VCCT4/5 139 TPFON5 140 TPFOP5 141 GNDR5 142 TPFIN5 143 TPFIP5 144 VCCR5 145 VCCR6 146 TPFIP6 147 TPFIN6 148 ...
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Table 1. RMII PQFP Pin List (Continued) Pin Symbol 170 TCK 171 TRST 172 N/C 173 G_FX/TP 174 PWRDWN 175 RESET 176 Section 177 ModeSel0 178 ModeSel1 179 SGND 180 LED4_1 181 LED4_2 182 LED4_3 183 GNDD 184 VCCD 185 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 1. RMII PQFP Pin List (Continued) Pin Symbol 204 TXD7_1 205 RXD6_1 206 RXD6_0 207 GNDIO 208 VCCIO 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri- State-able ...
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Table 2. SMII PQFP Pin List Pin Symbol 1 N/C 2 N/C 3 N/C 4 TXD6 5 N/C 6 REFCLK1 7 N/C 8 RXD5 9 GNDIO 10 N/C 11 N/C 12 N/C 13 TXD5 14 N/C 15 N/C 16 RXD4 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 2. SMII PQFP Pin List (Continued) Pin Symbol 34 TXD3 35 SYNC0 36 N/C 37 RXD2 38 GNDIO 39 N/C 40 N/C 41 N/C 42 TXD2 43 N/C 44 REFCLK0 45 N/C 46 ...
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Table 2. SMII PQFP Pin List (Continued) Pin Symbol 68 LED3_3 69 LED3_2 70 LED3_1 71 LED2_3 72 LED2_2 73 LED2_1 74 GNDIO 75 LED1_3 76 LED1_2 77 LED1_1 78 VCCD 79 GNDD 80 LED0_3 81 LED0_2 82 LED0_1 83 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 2. SMII PQFP Pin List (Continued) Pin Symbol 102 N/C 103 VCCR0 104 TPFIP0 105 TPFIN0 106 GNDR0 107 TPFOP0 108 TPFON0 109 VCCT0/1 110 TPFON1 111 TPFOP1 112 GNDR1 113 GNDT0/1 114 ...
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Table 2. SMII PQFP Pin List (Continued) Pin Symbol 136 TPFOP4 137 TPFON4 138 VCCT4/5 139 TPFON5 140 TPFOP5 141 GNDR5 142 TPFIN5 143 TPFIP5 144 VCCR5 145 VCCR6 146 TPFIP6 147 TPFIN6 148 GNDT6/7 149 GNDR6 150 TPFOP6 151 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 2. SMII PQFP Pin List (Continued) Pin Symbol 170 TCK 171 TRST 172 N/C 173 G_FX/TP 174 PWRDWN 175 RESET 176 Section 177 ModeSel0 178 ModeSel1 179 SGND 180 LED4_1 181 LED4_2 182 ...
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Table 2. SMII PQFP Pin List (Continued) Pin Symbol 204 SYNC1 205 N/C 206 RXD6 207 GNDIO 208 VCCIO 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri- State-able output, SL=Slew-rate Limited output, IP=Weak Internal ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 3. SS-SMII PQFP Pin List Pin Symbol 1 N/C 2 N/C 3 N/C 4 TXD6 5 N/C 6 REFCLK1 7 RXD5 8 N/C 9 GNDIO 10 N/C 11 N/C 12 N/C 13 TXD5 ...
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Table 3. SS-SMII PQFP Pin List (Continued) Pin Symbol 34 TXD3 35 TX_SYNC0 36 RXD2 37 N/C 38 GNDIO 39 N/C 40 N/C 41 N/C 42 TXD2 43 N/C 44 REFCLK0 45 RXD1 46 N/C 47 VCCIO 48 GNDIO 49 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 3. SS-SMII PQFP Pin List (Continued) Pin Symbol 68 LED3_3 69 LED3_2 70 LED3_1 71 LED2_3 72 LED2_2 73 LED2_1 74 GNDIO 75 LED1_3 76 LED1_2 77 LED1_1 78 VCCD 79 GNDD 80 ...
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Table 3. SS-SMII PQFP Pin List (Continued) Pin Symbol 102 N/C 103 VCCR0 104 TPFIP0 105 TPFIN0 106 GNDR0 107 TPFOP0 108 TPFON0 109 VCCT0/1 110 TPFON1 111 TPFOP1 112 GNDR1 113 GNDT0/1 114 TPFIN1 115 TPFIP1 116 VCCR1 117 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 3. SS-SMII PQFP Pin List (Continued) Pin Symbol 136 TPFOP4 137 TPFON4 138 VCCT4/5 139 TPFON5 140 TPFOP5 141 GNDR5 142 TPFIN5 143 TPFIP5 144 VCCR5 145 VCCR6 146 TPFIP6 147 TPFIN6 148 ...
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Table 3. SS-SMII PQFP Pin List (Continued) Pin Symbol 170 TCK 171 TRST 172 N/C 173 G_FX/TP 174 PWRDWN 175 RESET 176 Section 177 ModeSel0 178 ModeSel1 179 SGND 180 LED4_1 181 LED4_2 182 LED4_3 183 GNDD 184 VCCD 185 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 3. SS-SMII PQFP Pin List (Continued) Pin Symbol 204 TX_SYNC1 205 RXD6 206 N/C 207 GNDIO 208 VCCIO 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri- State-able ...
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Signal Name Conventions Signal names may contain either a port designation or a serial designation combination of the two designations. Signal naming conventions are as follows: • Port Number Only. Individual signals that apply to a particular ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 4. LXT9785 RMII Signal Descriptions (Continued) Pin-Ball Designation Symbol PQFP PBGA 60 E3, TXEN0 51 B2, TXEN1 41 C6, TXEN2 33 A7, TXEN3 21 B11, TXEN4 12 A14, TXEN5 3 C14, TXEN6 202 ...
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Table 5. LXT9785 SMII / SS-SMII Common Signal Descriptions Pin/Ball Designation Symbol Type PQFP PBGA 61 E2, TXD0 52 C3, TXD1 42 B5, TXD2 34 D8, TXD3 A11, TXD4 13 B13, TXD5 4 D13, TXD6 203 E14 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 7. LXT9785 SS-SMII Specific Signal Descriptions Pin/Ball Designation Symbol PQFP PBGA 35 A6, TX_SYNC0 204 C16 TX_SYNC1 RX_SYNC0 58 E4, 17 B12 RX_SYNC1 32 C8, TX_CLK0 201 D17 TX_CLK1 60 E3, RX_CLK0 21 ...
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Table 8. MDIO Control Interface Signals Pin/Ball Designation Symbol PQFP PBGA 64 F3, MDIO0 I/O, TS, SL, 25 A10 MDIO1 IP 67 F1, MDINT0 OD,TS, SL MDINT1 IP 63 E1, MDC0 I, ST B10 MDC1 84 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 9. LXT9785 Signal Detect Pin/Ball Designation Symbol PQFP PBGA 95 P1 SD_2P5V I, ST P2, SD0 97 N4, SD1 100 P3, SD2 101 N5, SD3 I 161 P15, SD4 162 P16, ...
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Table 11. LXT9785 JTAG Test Signal Descriptions Pin/Ball Designation Symbol PQFP PBGA 167 N14 TDI I, ST, IP 168 N15 TDO O, TS 169 N16 TMS I, ST, IP 170 M16 TCK I, ST, ID 171 M17 TRST I, ST, ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 12. LXT9785 Miscellaneous Signal Descriptions Pin/Ball Designation Symbol PQFP PBGA TxSLEW_0 94 N3 TxSLEW_1 50 D5 PAUSE 174 L14 PWRDWN 175 M15 RESET 88 L4, ADD_4 89 M2, ADD_3 90 M3, ...
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Table 12. LXT9785 Miscellaneous Signal Descriptions (Continued) Pin/Ball Designation Symbol PQFP PBGA 176 L15 SECTION 83 K1 AMDIX_EN 59 D2 MDIX 85 L2, CFG_3 86 L3, CFG_2 87 M1 CFG_1 173 M14 G_FX/TP 1. Type Column Coding Input, ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 13. LXT9785 LED Signal Descriptions Pin/Ball Designation Symbol PQFP PBGA 82 K3, LED0_1 81 K2, LED0_2 80 J1 LED0_3 77 J4, LED1_1 76 J3, LED1_2 75 H1 LED1_3 73 H2, LED2_1 72 H3, ...
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Table 14. LXT9785 Power Supply Signal Descriptions Pin/Ball Designation Symbol PQFP PBGA 65, 78, 184, G13, J14, VCCD 196 F5, J5 A2, A8, 18, 29, 47, C1, C11, VCCIO 56, 208 D14 98, 164 L13, L5 VCCPECL 103, 116, N13, ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 15. Unused / Reserved Pins Pin/Ball Designation Symbol PQFP PBGA F15, G2, G5, G14, G16, H4, N/C N/C H14, J2, J13, K4, K15 1. Type Column Coding Input Output, ...
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Functional Description 2.1 Introduction The LXT9785 is an 8-port Fast Ethernet 10/100 PHY transceiver that supports 10Mbps and 100Mbps networks, complying with all applicable requirements of IEEE 802.3 standards. The device incorporates a Serial MII (SMII), Source Synchronous SMII ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.1.2.1 Sectionalization The LXT9785’s sectional design allows flexibility with large multiport MACs and ASICs. With the use of the Section pin, the LXT9785 can be configured into a single 8-port or two separate 4-port ...
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Twisted-Pair Interface The LXT9785 supports either 100BASE-TX or 10BASE-T connections over 100 Unshielded Twisted-Pair (UTP). Only a transformer, load resistors, RJ-45, and bypass capacitors are required to complete this interface. Using Intel’s patented waveshaping technology, the transmitter shapes the ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.3.1 Global MII Mode Select The mode select pins are used for MII interface configuration settings upon power-up sequencing. All ports are configured the same and cannot be intermixed. Table 17. MII Mode Select ...
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One SYNC control stream is sourced by the MAC to the PHY. Both the transmit and receive data streams are segmented into boundaries delimited by the SYNC pulses. This interface is expected to operate inches ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 10. Management Interface Read Frame Structure MDC MDIO 32 "1" (Read) High Z Preamble ST Op Code Figure 11. Management Interface Write Frame Structure MDC MDIO 32 "1"s 0 ...
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MII Sectionalization When sectionalized into two quad sections, the MDIO bus splits into two separate PHY access ports. Ports 0-3 of the MDIO section operate independently of ports 4-7. The MII isolate function is unaffected and operates normally. Sectionalization ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.4 Operating Requirements 2.4.1 Power Requirements The LXT9785 requires four power supply inputs: VCCD, VCCA, VCCPECL and VCCIO. The digital and analog circuits require 2.5V supplies (VCCD, VCCR, and VCCT). These inputs may be ...
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Initialization When the LXT9785 is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 14. Initialization Sequence MDIO Control Mode Pass Control to MDIO Interface Software Reset? Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset 2.5.3 Power-Down Mode The LXT9785 incorporates ...
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All outputs are tri-stated. • All weak pad pull-up and pull-down resistors are disabled. • The MDIO registers are not accessible. • Configuration pins are not read upon release of the PWRDWN pin, and registers are reloaded with the ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.5.5 Hardware Configuration Settings The LXT9785 provides a hardware option to set the initial device configuration. The hardware option uses three Global CFG pins that provide control for all ports (see Table 18. Global ...
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This information is useful for recognizing when next pages must be re-sent due to the start of a new negotiation process. Bit 16.1 and the page received bit are also cleared ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.7 Serial MII Operation The LXT9785 exchanges transmit and receive data with the controller via the Serial MII (SMII). The SMII performs the following functions: • Conveys complete MII information between a 10/100 PHY ...
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Figure 16. Typical SMII Interface Diagram 125 MHz Sourced Externally or from Switch ASIC Datasheet Advanced 10/100 8-Port PHY — LXT9785 Typical SMII Interface in a 16-Port System SECTION 8 TxDatan SYNC0 8 RxDatan MDIO0 MDC0 MDINT0 RefCLK0 RefCLK1 SYSTEM ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 17. Typical SMII Quad Sectionalization Diagram 125 MHz Sourced Externally or from Switch ASIC 66 Typical SMII Interface in a 24-Port System RefClk0 RefClk1 8 TxDatan SYNC0 8 RxDatan MDIO0 MDC0 MDINT0 SECTION ...
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Figure 18. 100Mbps Serial MII Data Flow Serial Data Stream To/From MAC 2.7.1 SMII Reference Clock The REFCLK operates at 125 MHz. The transmit and receive data and control streams ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 19. Serial MII Transmit Synchronization CLOCK TxSYNC TX TX_ER TX_EN 2.7.4 Receive Data Stream Receive data and control information are signalled in ten- bit segments. In 100Mbps mode, each segment contains a new ...
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Figure 20. Serial MII Receive Synchronization CLOCK RxSYNC RX CRS Table 20. RX Status Encoding Bit Definitions Signal CRS Carrier Sense - identical to MII, except that it is not an asynchronous signal. Receive Data Valid - identical to MII. ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.7.5.1 Source Synchronous SMII Some system designs require the PHY to be placed between inches away from the MAC. A new source synchronous SMII definition has been added because of this ...
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Figure 21. Typical SS-SMII Interface Diagram 125 MHz Sourced Externally or from Switch ASIC Note: For SMII operation TxCLK1, RxSYNCn and RxCLKn pins are ignored Datasheet Advanced 10/100 8-Port PHY — LXT9785 Typical SS-SMII Interface in a 16-Port System SECTION ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 22. Typical SS-SMII Quad Sectionalization Diagram 125 MHz Sourced Externally or from Switch ASIC 72 Typical SS-SMII Interface in a 24-Port System RefClk0 RefClk1 8 TxDatan TxSYNC0 TxCLK0 8 RxDatan RxSYNC1 RxCLK1 MDIO0 ...
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Figure 23. Source Synchronous Transmit Timing TxCLK TxSYNC TxData TxCLK TxSYNC TxData Figure 24. Source Synchronous Receive Timing Datasheet Advanced 10/100 8-Port PHY — LXT9785 SS-SMII Transmit Timing TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXER Frcerr Speed TXEN ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.8 RMII Operation The LXT9785 provides an independent Reduced MII port for each network port. Each RMII uses four signals to pass received data to the MAC: RXDn<1:0>, RXERn, and CRS_DVn (where n reflects ...
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Figure 25. RMII Data Flow Reduced MII Mode Data Flow Parallel to Serial Serial to di-bit Parallel pairs Datasheet Advanced 10/100 8-Port PHY — LXT9785 4B/5B 4-bit ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 26. Typical RMII Interface Diagram 50 Mhz Sourced Externally or from Switch ASIC 76 Typical RMII Interface in a 16-Port System SECTION 8 TxD0n 8 TxD1n 8 TxENn 8 RxD0n 8 RxD1n 8 ...
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Figure 27. Typical RMII Quad Sectionalization Diagram 50 MHz Sourced Externally or from Switch ASIC Datasheet Advanced 10/100 8-Port PHY — LXT9785 Typical RMII Interface in a 24-Port System RefClk0 RefClk1 8 TxD0n 8 TxD1n 8 TxENn 8 RxD0n 8 ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.9 100Mbps Operation 2.9.1 100BASE-X Network Operations During 100BASE-X operation, the LXT9785 transmits and receives 5-bit symbols across the network link. Figure 28 actively transmitting data, the LXT9785 sends out Idle symbols on the ...
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Preamble Handling When the MAC asserts TXEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-of- Stream Delimiter (SSD), for the first two nibbles received across the RMII. The PCS layer continues to encode the remaining RMII ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.9.3 PMA Sublayer Table 22. 4B/5B Coding 4B Code Code Type ...
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Link In 100Mbps mode, the LXT9785 establishes a link whenever the scrambler becomes locked and remains locked for approximately 50 ms. Whenever the scrambler loses lock (<12 consecutive idle symbols during window), the link is taken down. ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.9.3.1 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as receiving, polarity correction, and ...
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In response to locally detected signal faults (SD activated by the local fiber transceiver), the affected port can transmit the far end fault code if fault code transmission is enabled by bit 16.2. • When bit 16 transmission ...
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LXT9785 — Advanced 10/100 8-Port PHY 2.10.3.1 Link Failure Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT9785 returns to the auto-negotiation phase if auto-negotiation is enabled. ...
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The LED driver pins are open drain circuits (10mA max current rating). Refer to page 90 under the Application Information Section for LED circuit design details. The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 31. RMII Programmable Out-of-Bank Signaling REFCLK CRS_DV RXD(1) sta tus 1 status 1 0s RXD(0) sta tus 0 status When network activity is detected, the LXT9785 asserts CRS_DV asynchronously with ...
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Boundary Scan Register Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the serial shift stage and the parallel output stage. There are four modes of operation as listed in 23. ...
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LXT9785 — Advanced 10/100 8-Port PHY 3.0 Application Information 3.1 Design Recommendations The LXT9785 is designed to comply with IEEE 802.3 requirements to provide outstanding receive Bit Error Rate (BER), and long-line-length performance. To achieve maximum performance from the LXT9785, ...
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Intel recommends filtering the power supply to the analog VCC pins of the LXT9785. This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT9785, helping with line performance. Second, if the VCC ...
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LXT9785 — Advanced 10/100 8-Port PHY 3.2.4 Twisted-Pair Interface Use the following standard guidelines for a twisted-pair interface: • Place the magnetics as close as possible to the LXT9785. • Keep transmit pair traces as short as possible; both traces ...
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Figure 32. LED Circuit V LED R LEDn_m Outside Inside 3 Volts +/- 5% LED Table 25. Magnetics Requirements Parameter Rx turns ratio Tx turns ratio Insertion loss Primary inductance Transformer isolation Differential to ...
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LXT9785 — Advanced 10/100 8-Port PHY 3.3 Typical Application Circuits Figure 33 through Figure 35 Figure 33. Power and Ground Supply Connections 92 show typical application circuits for the LXT9785. SGND GNDR/GNDT 0.01 F VCCR/VCCT Analog Supply Plane LXT9785 Digital ...
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Figure 34. Typical Twisted-Pair Interface LXT9785 1. The 100 transmit load termination resistor typically required is integrated in the LXT9785. 2. The 100 receive load termination resistor typically required is integrated in the LXT9785. Figure 35. Typical Fiber Interface TPFONn ...
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LXT9785 — Advanced 10/100 8-Port PHY 4.0 Test Specifications Note: Table 26 through Table 55 the LXT9785. These specifications are not guaranteed and are subject to change without notice. Minimum and maximum values listed in operating conditions specified in Table ...
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Table 27. Operating Conditions (Continued) Parameter 100BASE-TX 100BASE-FX Operating Current - SMII 10BASE-T Power-Down Mode Hardware Auto-Negotiation 100BASE-TX 100BASE-FX Operating Current - 10BASE-T SS-SMII Power-Down Mode Hardware Auto-Negotiation 1. Typical values are at 25 °C and are for design aid ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 29. Digital I/O Characteristics (VCCIO = 3.3V +/- 5%) Parameter Input Low voltage Input High voltage Input current Output Low voltage Output Low voltage (LEDm_n pins) Output High voltage Input Low voltage SD ...
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Table 32. 100BASE-FX Transceiver Characteristics Parameter Peak differential output voltage (single ended) Signal rise/fall time Jitter magnitude (measured differentially) Peak differential input voltage Common mode input range 1. Typical values are at 25 °C and are for design aid only; ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 36. SMII - 100BASE-TX Receive Timing REFCLK SYNC RXD TPFI Table 34. SMII - 100BASE-TX Receive Timing Parameters Parameter RXD output delay from REFCLK rising edge RXD Rise/Fall Time Receive start of /J/ ...
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Figure 37. SMII - 100BASE-TX Transmit Timing REFCLK SYNC TXD TPFO Table 35. SMII - 100BASE-TX Transmit Timing Parameters Parameter SYNC setup to REFCLK rising edge and TXD setup to REFCLK rising edge SYNC hold from REFCLK rising edge and ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 38. SMII - 100BASE-FX Receive Timing REFCLK SYNC RXD TPFI Table 36. SMII - 100BASE-FX Receive Timing Parameters Parameter RXD output delay from REFCLK rising edge RXD Rise/Fall Time Receive start of /J/ ...
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Figure 39. SMII - 100BASE-FX Transmit Timing REFCLK SYNC TXD TPFO Table 37. SMII - 100BASE-FX Transmit Timing Parameters Parameter SYNC setup to REFCLK rising edge and TXD setup to REFCLK rising edge SYNC hold from REFCLK rising edge and ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 40. SMII - 10BASE-T Receive Timing REFCLK SYNC RXD TPFI Table 38. SMII - 10BASE-T Receive Timing Parameters Parameter RXD output delay from REFCLK rising edge RXD Rise/Fall Time Receive Start-of-Frame to CRS ...
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Figure 41. SMII - 10BASE-T Transmit Timing REFCLK SYNC TXD TPFO Table 39. SMII-10BASE-T Transmit Timing Parameters Parameter SYNC setup to REFCLK rising edge and TXD setup to REFCLK rising edge SYNC hold to REFCLK rising edge and TXD hold ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 42. Source Synchronous SMII 100BASE-TX Receive Timing REFCLK RX_CLK RX_SYNC RXD TPFI Table 40. Source Synchronous SMII 100BASE-TX Receive Timing Parameters Parameter REFCLK rising edge to RX_CLK rising edge RXD/RX_SYNC output delay from ...
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Figure 43. Source Synchronous SMII 100BASE-TX Transmit Timing TX_CLK TX_SYNC TXD TPFO Table 41. Source Synchronous SMII 100BASE-TX Transmit Timing Parameter SYNC setup to TX_CLK rising edge and TXD setup to TX_CLK rising edge SYNC hold from TX_CLK rising edge ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 44. Source Synchronous SMII - 100BASE-FX Receive Timing REFCLK RX_CLK RX_SYNC RXD TPFI Table 42. Source Synchronous SMII - 100BASE-FX Receive Timing Parameters Parameter REFCLK rising edge to RxCLK rising edge RXD/RX_SYNC output ...
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Figure 45. Source Synchronous SMII - 100BASE-FX Transmit Timing TX_CLK TX_SYNC TXD TPFO Table 43. Source Synchronous SMII - 100BASE-FX Transmit Timing Parameters Parameter SYNC setup to REFCLK rising edge and TXD setup to REFCLK rising edge SYNC hold from ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 46. Source Synchronous SMII - 10BASE-T Receive Timing REFCLK RX_CLK RX_SYNC RXD TPFI Table 44. Source Synchronous SMII - 10BASE-T Receive Timing Parameters Parameter REFCLK rising edge to RX_CLK rising edge RXD/RX_SYNC output ...
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Figure 47. Source Synchronous SMII - 10BASE-T Transmit Timing TX_CLK TX_SYNC TXD TPFO Table 45. Source Synchronous SMII - 10BASE-T Transmit Timing Parameters Parameter TX_SYNC setup to TX_CLK rising edge and TXD setup to TX_CLK rising edge TX_SYNC hold to ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 48. RMII - 100BASE-TX Receive Timing REFCLK t 5 RXD(1:0) TPFI CRS_DV Table 46. RMII - 100BASE-TX Receive Timing Parameters Parameter RXD<1:0>/CRS_DV output delay from REFCLK 3 rising edge Receive start of /J/ ...
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Figure 49. RMII - 100BASE-TX Transmit Timing REFCLK TXD(1:0) TPFO t TX_EN Table 47. RMII - 100BASE-TX Transmit Timing Parameters Parameter TXD<1:0>/TX_EN setup to REFCLK rising edge TXD<1:0>/TX_EN hold from REFCLK rising edge TX_EN sampled to TPFO out (Tx latency) ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 50. RMII - 100BASE-FX Receive Timing REFCLK t RXD(1:0) TPFI CRS_DV Table 48. RMII - 100BASE-FX Receive Timing Parameters Parameter RXD<1:0>/CRS_DV output delay from REFCLK 3 rising edge Receive start of /J/ to ...
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Figure 51. RMII - 100BASE-FX Transmit Timing REFCLK TXD(1:0) TPFO TX_EN Table 49. RMII - 100BASE-FX Transmit Timing Parameters Parameter TXD<1:0>/TX_EN setup to REFCLK rising edge TXD<1:0>/TX-EN hold from REFCLK rising edge TX_EN sampled to TPFO out (Tx latency) 1. ...
Page 114
LXT9785 — Advanced 10/100 8-Port PHY Figure 52. RMII - 10BASE-T Receive Timing REFCLK RXD(1:0) TPFI CRS_DV Table 50. RMII - 10BASE-T Receive Timing Parameters Parameter RXD<1:0>/CRS_DV output delay from REFCLK 3 rising edge TPFI in to CRS_DV asserted TPFI ...
Page 115
Figure 53. RMII - 10BASE-T Transmit Timing REFCLK TXD(1:0) TPFO t TX_EN Table 51. RMII - 10BASE-T Transmit Timing Parameters Parameter TXD<1:0>/TX_EN setup to REFCLK rising edge TXD<1:0>/TX_EN hold from REFCLK rising edge TX_EN sampled to TPFO out (Tx latency) ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 54. Auto-Negotiation and Fast Link Pulse Timing TPFOP Figure 55. Fast Link Pulse Timing TPFOP Table 52. Auto-Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse ...
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Figure 56. MDIO Write Timing (MDIO Sourced by MAC) MDC MDIO Figure 57. MDIO Read Timing (MDIO Sourced by PHY) MDC MDIO Table 53. MDIO Timing Parameters Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced ...
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LXT9785 — Advanced 10/100 8-Port PHY Figure 58. Power-Up Timing Table 54. Power-Up Timing Parameters Parameter Voltage Threshold Power-Up recovery time 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to ...
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Register Definitions The LXT9785 register set includes multiple 16-bit registers, 17 registers per port. a complete register listing. provides a consolidated memory map of all registers. Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 57. Control Register (Address 0) Bit Name 0.15 Reset 0.14 Loopback 4 0.13 Speed Selection Auto-Negotiation 4 0.12 Enable 0.11 Power-Down 0.10 Isolate Restart 0.9 Auto-Negotiation 4 0.8 Duplex Mode 0.7 Collision Test ...
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Table 58. Status Register (Address 1) Bit Name 1.15 100BASE-T4 100BASE-X Full 1.14 Duplex 100BASE-X Half 1.13 Duplex 1.12 10Mbps Full Duplex 1.11 10Mbps Half Duplex 100BASE-T2 Full 1.10 Duplex 100BASE-T2 Half 1.9 Duplex 1.8 Extended Status 1.7 Reserved MF ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 59. PHY Identification Register 1 (Address 2) Bit Name 2.15:0 PHY ID Number Read Only Table 60. PHY Identification Register 2 (Address 3) Bit Name 3.15:10 PHY ID Number Manufacturer’s ...
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Table 61. Auto-Negotiation Advertisement Register (Address 4) Bit Name 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved Asymmetric 4.11 Pause 4.10 Pause 4.9 100BASE-T4 100BASE-TX 4.8 full duplex 4.7 100BASE-TX 10BASE-T 4.6 full duplex 4.5 10BASE-T Selector 4.4:0 ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 62. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) Bit Name 5.15 Next Page 5.14 Acknowledge 5.13 Remote Fault 5.12 Reserved Asymmetric 5.11 Pause 5.10 Pause 5.9 100BASE-T4 100BASE-TX 5.8 full duplex ...
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Table 63. Auto-Negotiation Expansion (Address 6) Bit Name 6.15:6 Reserved 6.5 Base Page Parallel 6.4 Detection Fault Link Partner 6.3 Next Page Able 6.2 Next Page Able 6.1 Page Received Link Partner A/ 6.0 N Able Read ...
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Table 65. Auto-Negotiation Link Partner Next Page Receive Register (Address 8) Bit Name Next Page 8.15 (NP) Acknowledge 8.14 (ACK) Message Page 8.13 (MP) Acknowledge 2 8.12 (ACK2) Toggle 8.11 (T) Message/ 8.10:0 Unformatted Code Field Read ...
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Table 66. Port Configuration Register (Address 16, Hex 10) Bit Name 16.15 Reserved 16.14 Link Disable 16.13 Transmit Disable Bypass Scramble 16.12 (100BASE-TX) Bypass 4B5B 16.11 (100BASE-TX) Jabber 16.10 (10BASE-T) SQE 16.9 (10BASE-T) TP Loopback 16.8 (10BASE-T) 16.7 Reserved 16.6 ...
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Table 67. Quick Status Register (Address 17, Hex 11) Bit Name 17.15 Reserved 17.14 10/100 Mode 17.13 Transmit Status 17.12 Receive Status 17.11 Collision Status 17.10 Link 17.9 Duplex Mode 17.8 Auto-Negotiation Auto-Negotiation 17.7 Complete 17.6 FIFO Error 17.5 Polarity ...
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Table 68. Interrupt Enable Register (Address 18, Hex 12) (Continued) Bit Name 18.6 SPEEDMSK 18.5 DUPLEXMSK 18.4 LINKMSK 18.3 ISOLMSK 18.2 Reserved 18.1 INTEN 18.0 TINT 1. R/W = Read/Write Datasheet Advanced 10/100 8-Port PHY — LXT9785 Description Mask for ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 69. Interrupt Status Register (Address 19, Hex 13) Bit Name 19.15:9 Reserved 19.8 RxERCntFUL 19.7 ANDONE 19.6 SPEEDCHG 19.5 DUPLEXCHG 19.4 LINKCHG 19.3 Isolate 19.2 MDINT 19.1 Reserved 19.0 Reserved 1. R/W = ...
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Table 70. LED Configuration Register (Address 20, Hex 14) Bit Name LED1 20.15:12 Programming bits LED2 20.11:8 Programming bits 1. R/W = Read/Write Read Only Latching High. 2. Link status is the primary LED driver. The ...
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LXT9785 — Advanced 10/100 8-Port PHY Table 70. LED Configuration Register (Address 20, Hex 14) (Continued) Bit Name LED3 20.7:4 Programming bits 20.3:2 LEDFREQ PULSE- 20.1 STRETCH 20.0 Reserved 1. R/W = Read/Write Read Only Latching ...
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Table 72. RMII Out-of-Band Signalling Register (Address 25) Bit Name 25:15:7 Reserved 25:6:4 BIT1 25.3:1 BIT0 25.0 PROGRMII 1. R/W = Read/Write RO = Read Only Table 73. Trim Enable Register (Address 27) Per-Port 27.11:10 Rise Time Control 27.9 AMDIX_EN ...
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Table 74. Register Bit Map Reg Title B15 B14 B13 B12 Speed A/N Control Reset Loopback Select Enable 100Base- 10Mbps 100Base-X Status 100Base-T4 X Full Full Half Duplex Duplex Duplex PHY PHY ID2 PHY ...
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Table 74. Register Bit Map (Continued) Reg Title B15 B14 B13 B12 Port Bypass Link Txmit Reserved Scrambler Config Disable Disable (100TX) Quick 10/100 Transmit Receiver Collision Reserved Status Mode Status Status Interrupt Reserved Enable Interrupt Reserved Status LED LED1 ...
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LXT9785 — Advanced 10/100 8-Port PHY 6.0 Package Specifications Figure 61. LXT9785 208-Pin PQFP Plastic Package Specification • • 136 208-Pin Plastic Quad Flat Package Part Number LXT9785HC Commercial Temperature ...
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... Figure 62. LXT9785 241-Ball PBGA Package Specification (LXT9785BC) Datasheet Advanced 10/100 8-Port PHY — LXT9785 137 ...
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